Commit 8b3e97ba authored by Lukas Auer's avatar Lukas Auer Committed by Andes
Browse files

riscv: add functions for reading the IPI status



Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).
Signed-off-by: default avatarLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: default avatarRick Chen <rick@andestech.com>
parent b86f6d1e
......@@ -117,6 +117,17 @@ int riscv_clear_ipi(int hart)
return 0;
}
int riscv_get_ipi(int hart, int *pending)
{
PLIC_BASE_GET();
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
*pending = !!(*pending & SEND_IPI_TO_HART(hart));
return 0;
}
static const struct udevice_id andes_plic_ids[] = {
{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
{ }
......
......@@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
return 0;
}
int riscv_get_ipi(int hart, int *pending)
{
/*
* The SBI does not support reading the IPI status. We always return 0
* to indicate that no IPI is pending.
*/
*pending = 0;
return 0;
}
......@@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
return 0;
}
int riscv_get_ipi(int hart, int *pending)
{
CLINT_BASE_GET();
*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
}
static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
{ }
......
......@@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart);
*/
extern int riscv_clear_ipi(int hart);
/**
* riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of hart to be checked
* @pending: Pointer to variable with result of the check,
* 1 if IPI is pending, 0 otherwise
* @return 0 if OK, -ve on error
*/
extern int riscv_get_ipi(int hart, int *pending);
static int send_ipi_many(struct ipi_data *ipi)
{
ofnode node, cpus;
......
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