Commit ac1ca999 authored by Tom Rini's avatar Tom Rini
Browse files
parents 0c5c3f29 2c4e067d
......@@ -99,6 +99,15 @@
device-name = "cpm-mdio";
};
cpm_xmdio: mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x16>;
status = "disabled";
device-name = "cpm-xmdio";
};
cpm_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
......
......@@ -99,6 +99,15 @@
device-name = "cps-mdio";
};
cps_xmdio: mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x16>;
status = "disabled";
device-name = "cps-xmdio";
};
cps_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
......
......@@ -336,13 +336,12 @@
reg = <0>;
/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-id";
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
};
......
......@@ -3,11 +3,18 @@
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/dma/k3-udma.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
ethernet0 = &cpsw_port1;
};
};
&cbass_main{
......@@ -24,6 +31,184 @@
clock-frequency = <25000000>;
u-boot,dm-spl;
};
mcu_conf: scm_conf@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_sel: cpsw-phy-sel@4040 {
compatible = "ti,am654-cpsw-phy-sel";
reg = <0x4040 0x4>;
reg-names = "gmii-sel";
};
};
cbass_mcu_navss: mcu_navss {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
dma-ranges;
ranges;
ti,sci-dev-id = <232>;
u-boot,dm-spl;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
u-boot,dm-spl;
};
mcu_udmap: udmap@31150000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
#dma-cells = <3>;
ti,ringacc = <&mcu_ringacc>;
ti,psil-base = <0x6000>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <236>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>; /* TX_HCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
u-boot,dm-spl;
};
};
mcu_cpsw: ethernet@046000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x46000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges;
dma-coherent;
clocks = <&k3_clks 18 22>;
clock-names = "fck";
power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
ti,psil-base = <0x7000>;
cpsw-phy-sel = <&phy_sel>;
dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
<&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
ports {
#address-cells = <1>;
#size-cells = <0>;
host: host@0 {
reg = <0>;
ti,label = "host";
};
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
ti,label = "port1";
ti,syscon-efuse = <&mcu_conf 0x200>;
};
};
davinci_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
};
cpts {
clocks = <&k3_clks 18 2>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
ti,psil-config0 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config1 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config2 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config3 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config4 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config5 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config6 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
ti,psil-config7 {
linux,udma-mode = <UDMA_PKT_MODE>;
statictr-type = <PSIL_STATIC_TR_NONE>;
ti,needs-epib;
ti,psd-size = <16>;
};
};
};
&secure_proxy_main {
......@@ -52,6 +237,29 @@
&wkup_pmx0 {
u-boot,dm-spl;
mcu_cpsw_pins_default: mcu_cpsw_pins_default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
>;
};
mcu_mdio_pins_default: mcu_mdio1_pins_default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
};
&main_pmx0 {
......@@ -73,3 +281,33 @@
&main_sdhci1 {
u-boot,dm-spl;
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};
&davinci_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
};
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
reg-names = "cpsw_nuss", "mac_efuse";
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
reg= <0x0 0x40f04040 0x0 0x4>;
reg-names = "gmii-sel";
};
};
......@@ -495,7 +495,7 @@ static int cboot_get_ethaddr_legacy(const void *fdt, uint8_t mac[ETH_ALEN])
return -ENOENT;
}
eth_parse_enetaddr(prop, mac);
string_to_enetaddr(prop, mac);
if (!is_valid_ethaddr(mac)) {
printf("Invalid MAC address: %s\n", prop);
......
......@@ -94,7 +94,7 @@ static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
unsigned char mac[6];
unsigned long val;
eth_parse_enetaddr(mac_string, mac);
string_to_enetaddr(mac_string, mac);
if (!channel)
ether = GETHER0_MAC_BASE;
......
......@@ -101,7 +101,7 @@ static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
unsigned char mac[6];
unsigned long val;
eth_parse_enetaddr(mac_string, mac);
string_to_enetaddr(mac_string, mac);
if (!channel)
ether = GETHER0_MAC_BASE;
......
......@@ -141,7 +141,7 @@ static void set_mac_to_sh_eth_register(int channel, char *mac_string)
unsigned char mac[6];
unsigned long val;
eth_parse_enetaddr(mac_string, mac);
string_to_enetaddr(mac_string, mac);
if (!channel)
ether = ETHER0_MAC_BASE;
......@@ -160,7 +160,7 @@ static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
unsigned char mac[6];
unsigned long val;
eth_parse_enetaddr(mac_string, mac);
string_to_enetaddr(mac_string, mac);
if (!channel)
ether = GETHER0_MAC_BASE;
......
......@@ -1473,8 +1473,22 @@ config CMD_NFS
config CMD_MII
bool "mii"
help
Enable MII utility commands.
imply CMD_MDIO
help
If set, allows 802.3(clause 22) MII Management functions interface access
The management interface specified in Clause 22 provides
a simple, two signal, serial interface to connect a
Station Management entity and a managed PHY for providing access
to management parameters and services.
The interface is referred to as the MII management interface.
config CMD_MDIO
bool "mdio"
depends on PHYLIB
help
If set, allows Enable 802.3(clause 45) MDIO interface registers access
The MDIO interface is orthogonal to the MII interface and extends
it by adding access to more registers through indirect addressing.
config CMD_PING
bool "ping"
......
......@@ -89,9 +89,7 @@ obj-$(CONFIG_CMD_MEMORY) += mem.o
obj-$(CONFIG_CMD_IO) += io.o
obj-$(CONFIG_CMD_MFSL) += mfsl.o
obj-$(CONFIG_CMD_MII) += mii.o
ifdef CONFIG_PHYLIB
obj-$(CONFIG_CMD_MII) += mdio.o
endif
obj-$(CONFIG_CMD_MDIO) += mdio.o
obj-$(CONFIG_CMD_MISC) += misc.o
obj-$(CONFIG_CMD_MMC) += mmc.o
obj-$(CONFIG_MP) += mp.o
......
......@@ -864,7 +864,7 @@ static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc,
return 0;
}
eth_parse_enetaddr(argv[*argc_nr + 1], parsed_cmd->ethaddr);
string_to_enetaddr(argv[*argc_nr + 1], parsed_cmd->ethaddr);
if (is_broadcast_ethaddr(parsed_cmd->ethaddr)) {
memset(parsed_cmd->ethaddr, 0xFF, sizeof(parsed_cmd->ethaddr));
......
......@@ -361,7 +361,7 @@ ulong env_get_hex(const char *varname, ulong default_val)
int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
{
eth_parse_enetaddr(env_get(name), enetaddr);
string_to_enetaddr(env_get(name), enetaddr);
return is_valid_ethaddr(enetaddr);
}
......
......@@ -22,7 +22,7 @@
#include "pxe_utils.h"
#define MAX_TFTP_PATH_LEN 127
#define MAX_TFTP_PATH_LEN 512
bool is_pxe;
......
......@@ -51,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
......@@ -61,6 +62,8 @@ CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
......@@ -79,6 +82,10 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_HBMC_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
......@@ -93,6 +100,7 @@ CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
......
......@@ -76,12 +76,12 @@ To assist in the management of these layers, a few helper functions exist. You
should use these rather than attempt to do any kind of parsing/manipulation
yourself as many common errors have arisen in the past.
* void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
* void string_to_enetaddr(const char *addr, uchar *enetaddr);
Convert a string representation of a MAC address to the binary version.
char *addr = "00:11:22:33:44:55";
uchar enetaddr[6];
eth_parse_enetaddr(addr, enetaddr);
string_to_enetaddr(addr, enetaddr);
/* enetaddr now equals { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 } */
* int eth_env_get_enetaddr(char *name, uchar *enetaddr);
......
PHY nodes for Aquantia devices.
This text describes properties that are applicable to Aquantia PHY nodes in
addition to the bindings in phy.txt.
Aquantia PHYs allow some flexibility in the way they are wired in a system,
they allow MDI pins to be reversed, LEDs linked up in different weays, have an
I2C slave interface that can be used for debug. Normally the configuration
corresponding to these is driven by the PHY firmware with the downside that
a custom firmware is needed for each integration of a PHY.
Several optional bindings are defined that allow these configuration points to
be driven by the PHY driver and reduce dependency on specific FW versions.
Optional properties:
mdi-reversal: 0 or 1 indicating that reversal must be disabled/enabled.
Firmware default is used if the property is missing.
smb-addr: I2C/SMBus address to use, firmware default is used if the property
is missing.
Example node:
phy@00 {
reg = <0x00>;
mdi-reversal = <1>;
smb-addr = <0x25>;
};
PHY nodes
If the device tree is used to describe networking interfaces, U-Boot expects a
node for each PHY. Parent node for such a PHY node is expected to correspond to
a MDIO bus and the bus is used to access the PHY.
Required properties:
- reg : The ID number for the phy, usually a small integer
Example:
ethernet-phy@0 {
compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
interrupt-parent = <&PIC>;
interrupts = <35 IRQ_TYPE_EDGE_RISING>;
reg = <0>;
resets = <&rst 8>;
reset-names = "phy";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <2000>;
};
......@@ -12,8 +12,10 @@ Required properties:
compensate for the board being designed with the lanes swapped.
- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
TX/RX lanes.
- ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
for applicable values. The CLK_OUT pin can also
be disabled by this property. When omitted, the
PHY's default will be left as is.
Default child nodes are standard Ethernet PHY device
nodes as described in doc/devicetree/bindings/net/ethernet.txt
......
......@@ -187,6 +187,18 @@ int dma_send(struct dma *dma, void *src, size_t len, void *metadata)
return ops->send(dma, src, len, metadata);
}
int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->get_cfg)
return -ENOSYS;
return ops->get_cfg(dma, cfg_id, cfg_data);
}
#endif /* CONFIG_DMA_CHANNELS */
int dma_get_device(u32 transfer_type, struct udevice **devp)
......
......@@ -104,6 +104,8 @@ struct udma_chan {
struct udma_rchan *rchan;
struct udma_rflow *rflow;
struct ti_udma_drv_chan_cfg_data cfg_data;
u32 bcnt; /* number of bytes completed since the start of the channel */
bool pkt_mode; /* TR or packet */
......@@ -1407,6 +1409,11 @@ static int udma_request(struct dma *dma)
uc->desc_rx_cur = 0;
uc->num_rx_bufs = 0;
if (uc->dir == DMA_DEV_TO_MEM) {
uc->cfg_data.flow_id_base = uc->rflow->id;
uc->cfg_data.flow_id_cnt = 1;
}
return 0;
}
......@@ -1689,6 +1696,26 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
return 0;
}
static int udma_get_cfg(struct dma *dma, u32 id, void **data)
{
struct udma_dev *ud = dev_get_priv(dma->dev);
struct udma_chan *uc;
if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
return -EINVAL;
}
switch (id) {
case TI_UDMA_CHAN_PRIV_INFO:
uc = &ud->channels[dma->id];
*data = &uc->cfg_data;
return 0;
}
return -EINVAL;
}
static const struct dma_ops udma_ops = {
.transfer = udma_transfer,
.of_xlate = udma_of_xlate,
......@@ -1699,10 +1726,12 @@ static const struct dma_ops udma_ops = {
.send = udma_send,
.receive = udma_receive,
.prepare_rcv_buf = udma_prepare_rcv_buf,
.get_cfg = udma_get_cfg,
};
static const struct udevice_id udma_ids[] = {
{ .compatible = "ti,k3-navss-udmap" },
{ .compatible = "ti,j721e-navss-mcu-udmap" },
{ }
};
......