Commit d9ea0d77 authored by Ian Ray's avatar Ian Ray Committed by Stefano Babic
Browse files

board: ge: bx50v3: correct LDB clock



Use Video PLL to provide 65MHz for all displays.
Signed-off-by: Ian Ray's avatarIan Ray <ian.ray@ge.com>
Signed-off-by: default avatarFabien Lahoudere <fabien.lahoudere@collabora.com>
parent 6ee7bb52
...@@ -426,14 +426,22 @@ static void enable_videopll(void) ...@@ -426,14 +426,22 @@ static void enable_videopll(void)
setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
/* set video pll to 910MHz (24MHz * (37+11/12)) /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
* video pll post div to 910/4 = 227.5MHz * |
*/ * PLL5
* |
* CS2CDR[LDB_DI0_CLK_SEL]
* |
* +----> LDB_DI0_SERIAL_CLK_ROOT
* |
* +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
*/
clrsetbits_le32(&ccm->analog_pll_video, clrsetbits_le32(&ccm->analog_pll_video,
BM_ANADIG_PLL_VIDEO_DIV_SELECT | BM_ANADIG_PLL_VIDEO_DIV_SELECT |
BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0)); BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
...@@ -459,8 +467,8 @@ static void setup_display_b850v3(void) ...@@ -459,8 +467,8 @@ static void setup_display_b850v3(void)
enable_videopll(); enable_videopll();
/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
imx_setup_hdmi(); imx_setup_hdmi();
...@@ -507,7 +515,7 @@ static void setup_display_bx50v3(void) ...@@ -507,7 +515,7 @@ static void setup_display_bx50v3(void)
*/ */
mdelay(200); mdelay(200);
/* IPU1 DI0 clock is 480/7 = 68.5 MHz */ /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
/* Set LDB_DI0 as clock source for IPU_DI0 */ /* Set LDB_DI0 as clock source for IPU_DI0 */
...@@ -683,12 +691,8 @@ int board_early_init_f(void) ...@@ -683,12 +691,8 @@ int board_early_init_f(void)
setup_iomux_uart(); setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3) #if defined(CONFIG_VIDEO_IPUV3)
if (is_b850v3()) /* Set LDB clock to Video PLL */
/* Set LDB clock to Video PLL */ select_ldb_di_clock_source(MXC_PLL5_CLK);
select_ldb_di_clock_source(MXC_PLL5_CLK);
else
/* Set LDB clock to USB PLL */
select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
#endif #endif
return 0; return 0;
} }
......
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