kvm_host.h 50.6 KB
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 * Kernel-based Virtual Machine driver for Linux
 *
 * This header defines architecture specific interfaces, x86 version
 */

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#ifndef _ASM_X86_KVM_HOST_H
#define _ASM_X86_KVM_HOST_H
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#include <linux/types.h>
#include <linux/mm.h>
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#include <linux/mmu_notifier.h>
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#include <linux/tracepoint.h>
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#include <linux/cpumask.h>
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#include <linux/irq_work.h>
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#include <linux/irq.h>
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#include <linux/kvm.h>
#include <linux/kvm_para.h>
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#include <linux/kvm_types.h>
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#include <linux/perf_event.h>
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#include <linux/pvclock_gtod.h>
#include <linux/clocksource.h>
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#include <linux/irqbypass.h>
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#include <linux/hyperv.h>
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#include <asm/apic.h>
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#include <asm/pvclock-abi.h>
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#include <asm/desc.h>
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#include <asm/mtrr.h>
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#include <asm/msr-index.h>
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#include <asm/asm.h>
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#include <asm/kvm_page_track.h>
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#include <asm/kvm_vcpu_regs.h>
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#include <asm/hyperv-tlfs.h>
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#define __KVM_HAVE_ARCH_VCPU_DEBUGFS

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#define KVM_MAX_VCPUS 288
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#define KVM_SOFT_MAX_VCPUS 240
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#define KVM_MAX_VCPU_ID 1023
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#define KVM_USER_MEM_SLOTS 509
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/* memory slots that are not exposed to userspace */
#define KVM_PRIVATE_MEM_SLOTS 3
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#define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS)
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#define KVM_HALT_POLL_NS_DEFAULT 200000
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#define KVM_IRQCHIP_NUM_PINS  KVM_IOAPIC_NUM_PINS

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#define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
					KVM_DIRTY_LOG_INITIALLY_SET)

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/* x86-specific vcpu->requests bit members */
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#define KVM_REQ_MIGRATE_TIMER		KVM_ARCH_REQ(0)
#define KVM_REQ_REPORT_TPR_ACCESS	KVM_ARCH_REQ(1)
#define KVM_REQ_TRIPLE_FAULT		KVM_ARCH_REQ(2)
#define KVM_REQ_MMU_SYNC		KVM_ARCH_REQ(3)
#define KVM_REQ_CLOCK_UPDATE		KVM_ARCH_REQ(4)
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#define KVM_REQ_LOAD_MMU_PGD		KVM_ARCH_REQ(5)
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#define KVM_REQ_EVENT			KVM_ARCH_REQ(6)
#define KVM_REQ_APF_HALT		KVM_ARCH_REQ(7)
#define KVM_REQ_STEAL_UPDATE		KVM_ARCH_REQ(8)
#define KVM_REQ_NMI			KVM_ARCH_REQ(9)
#define KVM_REQ_PMU			KVM_ARCH_REQ(10)
#define KVM_REQ_PMI			KVM_ARCH_REQ(11)
#define KVM_REQ_SMI			KVM_ARCH_REQ(12)
#define KVM_REQ_MASTERCLOCK_UPDATE	KVM_ARCH_REQ(13)
#define KVM_REQ_MCLOCK_INPROGRESS \
	KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
#define KVM_REQ_SCAN_IOAPIC \
	KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
#define KVM_REQ_GLOBAL_CLOCK_UPDATE	KVM_ARCH_REQ(16)
#define KVM_REQ_APIC_PAGE_RELOAD \
	KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
#define KVM_REQ_HV_CRASH		KVM_ARCH_REQ(18)
#define KVM_REQ_IOAPIC_EOI_EXIT		KVM_ARCH_REQ(19)
#define KVM_REQ_HV_RESET		KVM_ARCH_REQ(20)
#define KVM_REQ_HV_EXIT			KVM_ARCH_REQ(21)
#define KVM_REQ_HV_STIMER		KVM_ARCH_REQ(22)
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#define KVM_REQ_LOAD_EOI_EXITMAP	KVM_ARCH_REQ(23)
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#define KVM_REQ_GET_VMCS12_PAGES	KVM_ARCH_REQ(24)
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#define KVM_REQ_APICV_UPDATE \
	KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
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#define KVM_REQ_TLB_FLUSH_CURRENT	KVM_ARCH_REQ(26)
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#define KVM_REQ_HV_TLB_FLUSH \
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	KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_NO_WAKEUP)
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#define CR0_RESERVED_BITS                                               \
	(~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
			  | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
			  | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))

#define CR4_RESERVED_BITS                                               \
	(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
			  | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
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			  | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
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			  | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
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			  | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
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			  | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
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#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)


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#define INVALID_PAGE (~(hpa_t)0)
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#define VALID_PAGE(x) ((x) != INVALID_PAGE)

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#define UNMAPPED_GVA (~(gpa_t)0)

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/* KVM Hugepage definitions for x86 */
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enum {
	PT_PAGE_TABLE_LEVEL   = 1,
	PT_DIRECTORY_LEVEL    = 2,
	PT_PDPE_LEVEL         = 3,
	/* set max level to the biggest one */
	PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL,
};
#define KVM_NR_PAGE_SIZES	(PT_MAX_HUGEPAGE_LEVEL - \
				 PT_PAGE_TABLE_LEVEL + 1)
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#define KVM_HPAGE_GFN_SHIFT(x)	(((x) - 1) * 9)
#define KVM_HPAGE_SHIFT(x)	(PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
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#define KVM_HPAGE_SIZE(x)	(1UL << KVM_HPAGE_SHIFT(x))
#define KVM_HPAGE_MASK(x)	(~(KVM_HPAGE_SIZE(x) - 1))
#define KVM_PAGES_PER_HPAGE(x)	(KVM_HPAGE_SIZE(x) / PAGE_SIZE)
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static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
{
	/* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */
	return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
		(base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
}

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#define KVM_PERMILLE_MMU_PAGES 20
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#define KVM_MIN_ALLOC_MMU_PAGES 64UL
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#define KVM_MMU_HASH_SHIFT 12
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#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
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#define KVM_MIN_FREE_MMU_PAGES 5
#define KVM_REFILL_PAGES 25
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#define KVM_MAX_CPUID_ENTRIES 80
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#define KVM_NR_FIXED_MTRR_REGION 88
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#define KVM_NR_VAR_MTRR 8
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#define ASYNC_PF_PER_VCPU 64

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enum kvm_reg {
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	VCPU_REGS_RAX = __VCPU_REGS_RAX,
	VCPU_REGS_RCX = __VCPU_REGS_RCX,
	VCPU_REGS_RDX = __VCPU_REGS_RDX,
	VCPU_REGS_RBX = __VCPU_REGS_RBX,
	VCPU_REGS_RSP = __VCPU_REGS_RSP,
	VCPU_REGS_RBP = __VCPU_REGS_RBP,
	VCPU_REGS_RSI = __VCPU_REGS_RSI,
	VCPU_REGS_RDI = __VCPU_REGS_RDI,
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#ifdef CONFIG_X86_64
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	VCPU_REGS_R8  = __VCPU_REGS_R8,
	VCPU_REGS_R9  = __VCPU_REGS_R9,
	VCPU_REGS_R10 = __VCPU_REGS_R10,
	VCPU_REGS_R11 = __VCPU_REGS_R11,
	VCPU_REGS_R12 = __VCPU_REGS_R12,
	VCPU_REGS_R13 = __VCPU_REGS_R13,
	VCPU_REGS_R14 = __VCPU_REGS_R14,
	VCPU_REGS_R15 = __VCPU_REGS_R15,
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#endif
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	VCPU_REGS_RIP,
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	NR_VCPU_REGS,
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	VCPU_EXREG_PDPTR = NR_VCPU_REGS,
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	VCPU_EXREG_CR0,
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	VCPU_EXREG_CR3,
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	VCPU_EXREG_CR4,
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	VCPU_EXREG_RFLAGS,
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	VCPU_EXREG_SEGMENTS,
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	VCPU_EXREG_EXIT_INFO_1,
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	VCPU_EXREG_EXIT_INFO_2,
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};

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enum {
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	VCPU_SREG_ES,
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	VCPU_SREG_CS,
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	VCPU_SREG_SS,
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	VCPU_SREG_DS,
	VCPU_SREG_FS,
	VCPU_SREG_GS,
	VCPU_SREG_TR,
	VCPU_SREG_LDTR,
};

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enum exit_fastpath_completion {
	EXIT_FASTPATH_NONE,
	EXIT_FASTPATH_SKIP_EMUL_INS,
};

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struct x86_emulate_ctxt;
struct x86_exception;
enum x86_intercept;
enum x86_intercept_stage;
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#define KVM_NR_MEM_OBJS 40

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#define KVM_NR_DB_REGS	4

#define DR6_BD		(1 << 13)
#define DR6_BS		(1 << 14)
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#define DR6_BT		(1 << 15)
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#define DR6_RTM		(1 << 16)
#define DR6_FIXED_1	0xfffe0ff0
#define DR6_INIT	0xffff0ff0
#define DR6_VOLATILE	0x0001e00f
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#define DR7_BP_EN_MASK	0x000000ff
#define DR7_GE		(1 << 9)
#define DR7_GD		(1 << 13)
#define DR7_FIXED_1	0x00000400
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#define DR7_VOLATILE	0xffff2bff
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#define PFERR_PRESENT_BIT 0
#define PFERR_WRITE_BIT 1
#define PFERR_USER_BIT 2
#define PFERR_RSVD_BIT 3
#define PFERR_FETCH_BIT 4
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#define PFERR_PK_BIT 5
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#define PFERR_GUEST_FINAL_BIT 32
#define PFERR_GUEST_PAGE_BIT 33
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#define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
#define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
#define PFERR_USER_MASK (1U << PFERR_USER_BIT)
#define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
#define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
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#define PFERR_PK_MASK (1U << PFERR_PK_BIT)
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#define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT)
#define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT)

#define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK |	\
				 PFERR_WRITE_MASK |		\
				 PFERR_PRESENT_MASK)
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/* apic attention bits */
#define KVM_APIC_CHECK_VAPIC	0
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/*
 * The following bit is set with PV-EOI, unset on EOI.
 * We detect PV-EOI changes by guest by comparing
 * this bit with PV-EOI in guest memory.
 * See the implementation in apic_update_pv_eoi.
 */
#define KVM_APIC_PV_EOI_PENDING	1
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struct kvm_kernel_irq_routing_entry;

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/*
 * We don't want allocation failures within the mmu code, so we preallocate
 * enough memory for a single page fault in a cache.
 */
struct kvm_mmu_memory_cache {
	int nobjs;
	void *objects[KVM_NR_MEM_OBJS];
};

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/*
 * the pages used as guest page table on soft mmu are tracked by
 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used
 * by indirect shadow page can not be more than 15 bits.
 *
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 * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access,
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 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp.
 */
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union kvm_mmu_page_role {
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	u32 word;
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	struct {
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		unsigned level:4;
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		unsigned gpte_is_8_bytes:1;
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		unsigned quadrant:2;
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		unsigned direct:1;
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		unsigned access:3;
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		unsigned invalid:1;
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		unsigned nxe:1;
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		unsigned cr0_wp:1;
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		unsigned smep_andnot_wp:1;
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		unsigned smap_andnot_wp:1;
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		unsigned ad_disabled:1;
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		unsigned guest_mode:1;
		unsigned :6;
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		/*
		 * This is left at the top of the word so that
		 * kvm_memslots_for_spte_role can extract it with a
		 * simple shift.  While there is room, give it a whole
		 * byte so it is also faster to load it from memory.
		 */
		unsigned smm:8;
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	};
};

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union kvm_mmu_extended_role {
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/*
 * This structure complements kvm_mmu_page_role caching everything needed for
 * MMU configuration. If nothing in both these structures changed, MMU
 * re-configuration can be skipped. @valid bit is set on first usage so we don't
 * treat all-zero structure as valid data.
 */
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	u32 word;
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	struct {
		unsigned int valid:1;
		unsigned int execonly:1;
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		unsigned int cr0_pg:1;
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		unsigned int cr4_pae:1;
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		unsigned int cr4_pse:1;
		unsigned int cr4_pke:1;
		unsigned int cr4_smap:1;
		unsigned int cr4_smep:1;
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		unsigned int maxphyaddr:6;
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	};
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};

union kvm_mmu_role {
	u64 as_u64;
	struct {
		union kvm_mmu_page_role base;
		union kvm_mmu_extended_role ext;
	};
};

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struct kvm_rmap_head {
	unsigned long val;
};

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struct kvm_mmu_page {
	struct list_head link;
	struct hlist_node hash_link;
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	struct list_head lpage_disallowed_link;

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	bool unsync;
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	u8 mmu_valid_gen;
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	bool mmio_cached;
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	bool lpage_disallowed; /* Can't be replaced by an equiv large page */
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	/*
	 * The following two entries are used to key the shadow page in the
	 * hash table.
	 */
	union kvm_mmu_page_role role;
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	gfn_t gfn;
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	u64 *spt;
	/* hold the gfn of each spte inside spt */
	gfn_t *gfns;
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	int root_count;          /* Currently serving as active root */
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	unsigned int unsync_children;
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	struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */
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	DECLARE_BITMAP(unsync_child_bitmap, 512);
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#ifdef CONFIG_X86_32
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	/*
	 * Used out of the mmu-lock to avoid reading spte values while an
	 * update is in progress; see the comments in __get_spte_lockless().
	 */
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	int clear_spte_count;
#endif

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	/* Number of writes since the last time traversal visited this page.  */
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	atomic_t write_flooding_count;
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};

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struct kvm_pio_request {
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	unsigned long linear_rip;
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	unsigned long count;
	int in;
	int port;
	int size;
};

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#define PT64_ROOT_MAX_LEVEL 5
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struct rsvd_bits_validate {
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	u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
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	u64 bad_mt_xwr;
};

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struct kvm_mmu_root_info {
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	gpa_t pgd;
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	hpa_t hpa;
};

#define KVM_MMU_ROOT_INFO_INVALID \
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	((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE })
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#define KVM_MMU_NUM_PREV_ROOTS 3

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/*
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 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
 * and 2-level 32-bit).  The kvm_mmu structure abstracts the details of the
 * current mmu mode.
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 */
struct kvm_mmu {
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	unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
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	u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
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	int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err,
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			  bool prefault);
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	void (*inject_page_fault)(struct kvm_vcpu *vcpu,
				  struct x86_exception *fault);
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	gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa,
			    u32 access, struct x86_exception *exception);
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	gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
			       struct x86_exception *exception);
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	int (*sync_page)(struct kvm_vcpu *vcpu,
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			 struct kvm_mmu_page *sp);
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	void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa);
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	void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
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			   u64 *spte, const void *pte);
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	hpa_t root_hpa;
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	gpa_t root_pgd;
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	union kvm_mmu_role mmu_role;
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	u8 root_level;
	u8 shadow_root_level;
	u8 ept_ad;
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	bool direct_map;
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	struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
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	/*
	 * Bitmap; bit set = permission fault
	 * Byte index: page fault error code [4:1]
	 * Bit index: pte permissions in ACC_* format
	 */
	u8 permissions[16];

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	/*
	* The pkru_mask indicates if protection key checks are needed.  It
	* consists of 16 domains indexed by page fault error code bits [4:1],
	* with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
	* Each domain has 2 bits which are ANDed with AD and WD from PKRU.
	*/
	u32 pkru_mask;

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	u64 *pae_root;
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	u64 *lm_root;
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	/*
	 * check zero bits on shadow page table entries, these
	 * bits include not only hardware reserved bits but also
	 * the bits spte never used.
	 */
	struct rsvd_bits_validate shadow_zero_check;

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	struct rsvd_bits_validate guest_rsvd_check;
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	/* Can have large pages at levels 2..last_nonleaf_level-1. */
	u8 last_nonleaf_level;
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	bool nx;

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	u64 pdptrs[4]; /* pae */
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};

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struct kvm_tlb_range {
	u64 start_gfn;
	u64 pages;
};

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enum pmc_type {
	KVM_PMC_GP = 0,
	KVM_PMC_FIXED,
};

struct kvm_pmc {
	enum pmc_type type;
	u8 idx;
	u64 counter;
	u64 eventsel;
	struct perf_event *perf_event;
	struct kvm_vcpu *vcpu;
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	/*
	 * eventsel value for general purpose counters,
	 * ctrl value for fixed counters.
	 */
	u64 current_config;
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};

struct kvm_pmu {
	unsigned nr_arch_gp_counters;
	unsigned nr_arch_fixed_counters;
	unsigned available_event_types;
	u64 fixed_ctr_ctrl;
	u64 global_ctrl;
	u64 global_status;
	u64 global_ovf_ctrl;
	u64 counter_bitmask[2];
	u64 global_ctrl_mask;
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	u64 global_ovf_ctrl_mask;
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	u64 reserved_bits;
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	u8 version;
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	struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
	struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
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	struct irq_work irq_work;
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	DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
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	DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
	DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);

	/*
	 * The gate to release perf_events not marked in
	 * pmc_in_use only once in a vcpu time slice.
	 */
	bool need_cleanup;

	/*
	 * The total number of programmed perf_events and it helps to avoid
	 * redundant check before cleanup if guest don't use vPMU at all.
	 */
	u8 event_count;
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};

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struct kvm_pmu_ops;

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enum {
	KVM_DEBUGREG_BP_ENABLED = 1,
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	KVM_DEBUGREG_WONT_EXIT = 2,
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	KVM_DEBUGREG_RELOAD = 4,
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};

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struct kvm_mtrr_range {
	u64 base;
	u64 mask;
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	struct list_head node;
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};

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struct kvm_mtrr {
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	struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
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	mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
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	u64 deftype;
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	struct list_head head;
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};

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/* Hyper-V SynIC timer */
struct kvm_vcpu_hv_stimer {
	struct hrtimer timer;
	int index;
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	union hv_stimer_config config;
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	u64 count;
	u64 exp_time;
	struct hv_message msg;
	bool msg_pending;
};

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/* Hyper-V synthetic interrupt controller (SynIC)*/
struct kvm_vcpu_hv_synic {
	u64 version;
	u64 control;
	u64 msg_page;
	u64 evt_page;
	atomic64_t sint[HV_SYNIC_SINT_COUNT];
	atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
	DECLARE_BITMAP(auto_eoi_bitmap, 256);
	DECLARE_BITMAP(vec_bitmap, 256);
	bool active;
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	bool dont_zero_synic_pages;
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};

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/* Hyper-V per vcpu emulation context */
struct kvm_vcpu_hv {
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	u32 vp_index;
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	u64 hv_vapic;
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	s64 runtime_offset;
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	struct kvm_vcpu_hv_synic synic;
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	struct kvm_hyperv_exit exit;
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	struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
	DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
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	cpumask_t tlb_flush;
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};

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struct kvm_vcpu_arch {
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	/*
	 * rip and regs accesses must go through
	 * kvm_{register,rip}_{read,write} functions.
	 */
	unsigned long regs[NR_VCPU_REGS];
	u32 regs_avail;
	u32 regs_dirty;
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	unsigned long cr0;
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	unsigned long cr0_guest_owned_bits;
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	unsigned long cr2;
	unsigned long cr3;
	unsigned long cr4;
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	unsigned long cr4_guest_owned_bits;
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	unsigned long cr8;
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	u32 host_pkru;
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	u32 pkru;
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	u32 hflags;
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	u64 efer;
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	u64 apic_base;
	struct kvm_lapic *apic;    /* kernel irqchip context */
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	bool apicv_active;
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	bool load_eoi_exitmap_pending;
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	DECLARE_BITMAP(ioapic_handled_vectors, 256);
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	unsigned long apic_attention;
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	int32_t apic_arb_prio;
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	int mp_state;
	u64 ia32_misc_enable_msr;
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	u64 smbase;
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	u64 smi_count;
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	bool tpr_access_reporting;
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	bool xsaves_enabled;
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	u64 ia32_xss;
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	u64 microcode_version;
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	u64 arch_capabilities;
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	/*
	 * Paging state of the vcpu
	 *
	 * If the vcpu runs in guest mode with two level paging this still saves
	 * the paging mode of the l1 guest. This context is always used to
	 * handle faults.
	 */
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	struct kvm_mmu *mmu;

	/* Non-nested MMU for L1 */
	struct kvm_mmu root_mmu;
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	/* L1 MMU when running nested */
	struct kvm_mmu guest_mmu;

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	/*
	 * Paging state of an L2 guest (used for nested npt)
	 *
	 * This context will save all necessary information to walk page tables
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	 * of an L2 guest. This context is only initialized for page table
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	 * walking and not for faulting since we never handle l2 page faults on
	 * the host.
	 */
	struct kvm_mmu nested_mmu;

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	/*
	 * Pointer to the mmu context currently used for
	 * gva_to_gpa translations.
	 */
	struct kvm_mmu *walk_mmu;

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	struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
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	struct kvm_mmu_memory_cache mmu_page_cache;
	struct kvm_mmu_memory_cache mmu_page_header_cache;

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	/*
	 * QEMU userspace and the guest each have their own FPU state.
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	 * In vcpu_run, we switch between the user and guest FPU contexts.
	 * While running a VCPU, the VCPU thread will have the guest FPU
	 * context.
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	 *
	 * Note that while the PKRU state lives inside the fpu registers,
	 * it is switched out separately at VMENTER and VMEXIT time. The
	 * "guest_fpu" state here contains the guest FPU context, with the
	 * host PRKU bits.
	 */
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	struct fpu *user_fpu;
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	struct fpu *guest_fpu;
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	u64 xcr0;
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	u64 guest_supported_xcr0;
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	u32 guest_xstate_size;
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	struct kvm_pio_request pio;
	void *pio_data;

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	u8 event_exit_inst_len;

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	struct kvm_queued_exception {
		bool pending;
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		bool injected;
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		bool has_error_code;
		u8 nr;
		u32 error_code;
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		unsigned long payload;
		bool has_payload;
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		u8 nested_apf;
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	} exception;

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	struct kvm_queued_interrupt {
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		bool injected;
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		bool soft;
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		u8 nr;
	} interrupt;

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	int halt_request; /* real mode on Intel only */

	int cpuid_nent;
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	struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
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	int maxphyaddr;

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	/* emulate context */

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	struct x86_emulate_ctxt *emulate_ctxt;
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	bool emulate_regs_need_sync_to_vcpu;
	bool emulate_regs_need_sync_from_vcpu;
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	int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
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	gpa_t time;
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	struct pvclock_vcpu_time_info hv_clock;
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	unsigned int hw_tsc_khz;
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	struct gfn_to_hva_cache pv_time;
	bool pv_time_enabled;
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	/* set guest stopped flag in pvclock flags field */
	bool pvclock_set_guest_stopped_request;
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	struct {
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		u8 preempted;
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		u64 msr_val;
		u64 last_steal;
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		struct gfn_to_pfn_cache cache;
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	} st;

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	u64 l1_tsc_offset;
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	u64 tsc_offset;
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	u64 last_guest_tsc;
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	u64 last_host_tsc;
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	u64 tsc_offset_adjustment;
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	u64 this_tsc_nsec;
	u64 this_tsc_write;
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	u64 this_tsc_generation;
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	bool tsc_catchup;
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	bool tsc_always_catchup;
	s8 virtual_tsc_shift;
	u32 virtual_tsc_mult;
	u32 virtual_tsc_khz;
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	s64 ia32_tsc_adjust_msr;
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	u64 msr_ia32_power_ctl;
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	u64 tsc_scaling_ratio;
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	atomic_t nmi_queued;  /* unprocessed asynchronous NMIs */
	unsigned nmi_pending; /* NMI queued after currently running handler */
	bool nmi_injected;    /* Trying to inject an NMI this entry */
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	bool smi_pending;    /* SMI queued after currently running handler */
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	struct kvm_mtrr mtrr_state;
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	u64 pat;
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	unsigned switch_db_regs;
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	unsigned long db[KVM_NR_DB_REGS];
	unsigned long dr6;
	unsigned long dr7;
	unsigned long eff_db[KVM_NR_DB_REGS];
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	unsigned long guest_debug_dr7;
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	u64 msr_platform_info;
	u64 msr_misc_features_enables;
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	u64 mcg_cap;
	u64 mcg_status;
	u64 mcg_ctl;
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	u64 mcg_ext_ctl;
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	u64 *mce_banks;
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	/* Cache MMIO info */
	u64 mmio_gva;
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	unsigned mmio_access;
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	gfn_t mmio_gfn;
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	u64 mmio_gen;
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	struct kvm_pmu pmu;

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	/* used for guest single stepping over the given code position */
	unsigned long singlestep_rip;
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	struct kvm_vcpu_hv hyperv;
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	cpumask_var_t wbinvd_dirty_mask;
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	unsigned long last_retry_eip;
	unsigned long last_retry_addr;

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	struct {
		bool halted;
		gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
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		struct gfn_to_hva_cache data;
		u64 msr_val;
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		u32 id;
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		bool send_user_only;
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		u32 host_apf_reason;
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		unsigned long nested_apf_token;
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		bool delivery_as_pf_vmexit;
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	} apf;
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	/* OSVW MSRs (AMD only) */
	struct {
		u64 length;
		u64 status;
	} osvw;
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	struct {
		u64 msr_val;
		struct gfn_to_hva_cache data;
	} pv_eoi;
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	u64 msr_kvm_poll_control;

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	/*
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	 * Indicates the guest is trying to write a gfn that contains one or
	 * more of the PTEs used to translate the write itself, i.e. the access
	 * is changing its own translation in the guest page tables.  KVM exits
	 * to userspace if emulation of the faulting instruction fails and this
	 * flag is set, as KVM cannot make forward progress.
	 *
	 * If emulation fails for a write to guest page tables, KVM unprotects
	 * (zaps) the shadow page for the target gfn and resumes the guest to
	 * retry the non-emulatable instruction (on hardware).  Unprotecting the
	 * gfn doesn't allow forward progress for a self-changing access because
	 * doing so also zaps the translation for the gfn, i.e. retrying the
	 * instruction will hit a !PRESENT fault, which results in a new shadow
	 * page and sends KVM back to square one.
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	 */
	bool write_fault_to_shadow_pgtable;
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	/* set at EPT violation at this point */
	unsigned long exit_qualification;
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	/* pv related host specific info */
	struct {
		bool pv_unhalted;
	} pv;
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	int pending_ioapic_eoi;
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	int pending_external_vector;
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	/* be preempted when it's in kernel-mode(cpl=0) */
	bool preempted_in_kernel;
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	/* Flush the L1 Data cache for L1TF mitigation on VMENTER */
	bool l1tf_flush_l1d;
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	/* AMD MSRC001_0015 Hardware Configuration */
	u64 msr_hwcr;
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};

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struct kvm_lpage_info {
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	int disallow_lpage;
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};

struct kvm_arch_memory_slot {
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	struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
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	struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
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	unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
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};

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/*
 * We use as the mode the number of bits allocated in the LDR for the
 * logical processor ID.  It happens that these are all powers of two.
 * This makes it is very easy to detect cases where the APICs are
 * configured for multiple modes; in that case, we cannot use the map and
 * hence cannot use kvm_irq_delivery_to_apic_fast either.
 */
#define KVM_APIC_MODE_XAPIC_CLUSTER          4
#define KVM_APIC_MODE_XAPIC_FLAT             8
#define KVM_APIC_MODE_X2APIC                16

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struct kvm_apic_map {
	struct rcu_head rcu;
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	u8 mode;
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	u32 max_apic_id;
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	union {
		struct kvm_lapic *xapic_flat_map[8];
		struct kvm_lapic *xapic_cluster_map[16][4];
	};
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	struct kvm_lapic *phys_map[];
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};

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/* Hyper-V emulation context */
struct kvm_hv {
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	struct mutex hv_lock;
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	u64 hv_guest_os_id;
	u64 hv_hypercall;
	u64 hv_tsc_page;
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	/* Hyper-v based guest crash (NT kernel bugcheck) parameters */
	u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
	u64 hv_crash_ctl;
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	HV_REFERENCE_TSC_PAGE tsc_ref;
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	struct idr conn_to_evt;
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	u64 hv_reenlightenment_control;
	u64 hv_tsc_emulation_control;
	u64 hv_tsc_emulation_status;
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	/* How many vCPUs have VP index != vCPU index */
	atomic_t num_mismatched_vp_indexes;
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	struct hv_partition_assist_pg *hv_pa_pg;
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};

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enum kvm_irqchip_mode {
	KVM_IRQCHIP_NONE,
	KVM_IRQCHIP_KERNEL,       /* created with KVM_CREATE_IRQCHIP */
	KVM_IRQCHIP_SPLIT,        /* created with KVM_CAP_SPLIT_IRQCHIP */
};

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#define APICV_INHIBIT_REASON_DISABLE    0
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#define APICV_INHIBIT_REASON_HYPERV     1
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#define APICV_INHIBIT_REASON_NESTED     2
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#define APICV_INHIBIT_REASON_IRQWIN     3
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#define APICV_INHIBIT_REASON_PIT_REINJ  4
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#define APICV_INHIBIT_REASON_X2APIC	5
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struct kvm_arch {
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	unsigned long n_used_mmu_pages;
	unsigned long n_requested_mmu_pages;
	unsigned long n_max_mmu_pages;
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	unsigned int indirect_shadow_pages;
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	u8 mmu_valid_gen;
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	struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
	/*
	 * Hash table of struct kvm_mmu_page.
	 */
	struct list_head active_mmu_pages;
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	struct list_head zapped_obsolete_pages;
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	struct list_head lpage_disallowed_mmu_pages;
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	struct kvm_page_track_notifier_node mmu_sp_tracker;
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	struct kvm_page_track_notifier_head track_notifier_head;
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	struct list_head assigned_dev_head;
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	struct iommu_domain *iommu_domain;
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	bool iommu_noncoherent;
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#define __KVM_HAVE_ARCH_NONCOHERENT_DMA
	atomic_t noncoherent_dma_count;
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#define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
	atomic_t assigned_device_count;
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	struct kvm_pic *vpic;
	struct kvm_ioapic *vioapic;
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	struct kvm_pit *vpit;
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	atomic_t vapics_in_nmi_mode;
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	struct mutex apic_map_lock;
	struct kvm_apic_map *apic_map;
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	bool apic_map_dirty;
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	bool apic_access_page_done;
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	unsigned long apicv_inhibit_reasons;
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	gpa_t wall_clock;
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	bool mwait_in_guest;
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	bool hlt_in_guest;
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	bool pause_in_guest;
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	bool cstate_in_guest;
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	unsigned long irq_sources_bitmap;
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	s64 kvmclock_offset;
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	raw_spinlock_t tsc_write_lock;
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	u64 last_tsc_nsec;
	u64 last_tsc_write;
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	u32 last_tsc_khz;
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	u64 cur_tsc_nsec;
	u64 cur_tsc_write;
	u64 cur_tsc_offset;
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	u64 cur_tsc_generation;
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	int nr_vcpus_matched_tsc;
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	spinlock_t pvclock_gtod_sync_lock;
	bool use_master_clock;
	u64 master_kernel_ns;
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	u64 master_cycle_now;
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	struct delayed_work kvmclock_update_work;
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	struct delayed_work kvmclock_sync_work;
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	struct kvm_xen_hvm_config xen_hvm_config;
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	/* reads protected by irq_srcu, writes by irq_lock */
	struct hlist_head mask_notifier_list;

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	struct kvm_hv hyperv;