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huang lin authored
we use npll as vop source clock in coreboot, and in kernel it will change the npll rate before vop initial, it may cause display corruption in some panel. so we reset the vop to stop display at the end of depthcharge. BUG=chrome-os-partner:34713 TEST=Boot from jerry, and display normal BRANCH=None Change-Id: I2aabf5a47b8254355a7f0980dc98f6e76bb9c064 Signed-off-by: huang lin <hl@rock-chips.com> Signed-off-by: zhengxing <zhengxing@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/239470 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Commit-Queue: Daniel Kurtz <djkurtz@chromium.org> Trybot-Ready: Daniel Kurtz <djkurtz@chromium.org>
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