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Daisuke Nojiri authored
When Depthcharge writes to flash through EC, it adds padding to make the data size equal to write_block_size of the SPI flash. Though this might be necessary for a certain board (Pit as described in CL:62895), this fails if we're writing to the end of the SPI flash because EC checks whether (offset + size) exceeds the flash size or not (legitimately). I think we should play this trick (padding to write block size) on the EC side. That is, if EC receives a short packet, it should add padding by itself if it's required. Pit has been removed from the crosEC tree. If this patch breaks another board, we'll fix it differently (as suggested above). BUG=chromiumos:756230 BRANCH=none TEST=Let Depthcharge on Fizz write a RW image to the slot B, which is located at the end. Change-Id: I2f51917976189ea01de8c5787f6329f0a45c7f74 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/618164 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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