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Shelley Chen authored
We are changing the bootstraps in the EVTs so that the SOC communicates with cr50 over SPI instead of cr50. SPI is more reliable than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI. BUG=b:65056998, b:62456589 BRANCH=None TEST=make sure that we can boot into kernel with a board reworked with SPI bootstraps. Test out both cold and warm reset. CQ-DEPEND=CL:718903 Change-Id: I8b8ab22f17be37ea25d44d11fb7466f598b33a05 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/714237 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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