Coreboot is taking a lot of effort reading device-tree values for
fall/rise time or lcnt/hcnt and calculating and configuring
controller register values to ensure I2C bus speed is within limits
when used in firmware. Depthcharge driver was resetting all those
values by using default configuration. This resulted in I2C bus speed
in depthcharge going beyond limits. (Noticed by sudden spike in H1 I2C
frequency in depthcharge).

This change updates the designware I2C driver to check if high and low
cycle time registers are already configured and skip initialization
of the bus completely.

BUG=b:35948024
BRANCH=eve
TEST=Verified that H1 I2C frequency is <400KHz in coreboot and in
depthcharge. No spikes observed after jumping to depthcharge. Also, no
errors seen while communicating with H1 in depthcharge.

Change-Id: Icc2d2d45710a203325d1780f80e2e8d024c8c9a4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/592550


Reviewed-by: Duncan Laurie <dlaurie@google.com>