Commit 26571a2c authored by Nick Vaccaro's avatar Nick Vaccaro Committed by chrome-bot

zoombini: Add support for new board

BUG=b:64395641
BRANCH=None
TEST="emerge-zoombini depthcharge" compiles successfully

Change-Id: Ia296ddf6dbdb0b94bb7088bc7b6ff755607adb3c
Signed-off-by: default avatarNick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/669958Reviewed-by: default avatarAaron Durbin <adurbin@chromium.org>
parent 902c4b71
# Arch
CONFIG_ARCH_X86=y
# Board
CONFIG_BOARD="zoombini"
# Image
CONFIG_FMAP_OFFSET=0x00C10000
CONFIG_HEAP_SIZE=0x00600000
# Vboot
CONFIG_TPM2_MODE=y
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_ACPI=y
CONFIG_NV_STORAGE_CMOS=y
CONFIG_TPM_DEBUG_EXTENSIONS=y
# Kernel format
CONFIG_KERNEL_ZIMAGE=y
# Drivers
CONFIG_DRIVER_BUS_I2C_DESIGNWARE=y
CONFIG_DRIVER_BUS_I2C_DESIGNWARE_PCI=y
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_LPC=y
CONFIG_DRIVER_FLASH_MEMMAPPED=y
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_BUS_SPI_INTEL_GSPI=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
CONFIG_DRIVER_STORAGE_SDHCI_PCI=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_TPM_SPI=y
##
## Copyright 2017 Google Inc. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## Copyright 2017 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
depthcharge-y += board.c
/*
* Copyright 2017 Google Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <libpayload.h>
#include <pci.h>
#include <pci/pci.h>
#include <sysinfo.h>
#include "base/init_funcs.h"
#include "base/list.h"
#include "config.h"
#include "drivers/bus/i2c/designware.h"
#include "drivers/bus/spi/intel_gspi.h"
#include "drivers/bus/usb/usb.h"
#include "drivers/ec/cros/lpc.h"
#include "drivers/flash/flash.h"
#include "drivers/flash/memmapped.h"
#include "drivers/gpio/sysinfo.h"
#include "drivers/power/pch.h"
#include "drivers/soc/cannonlake.h"
#include "drivers/storage/nvme.h"
#include "drivers/storage/blockdev.h"
#include "drivers/storage/sdhci.h"
#include "drivers/tpm/cr50_i2c.h"
#include "drivers/tpm/spi.h"
#include "drivers/tpm/tpm.h"
/*
* Clock frequencies for the eMMC and SD ports are defined below. The minimum
* frequency is the same for both interfaces, the firmware does not run any
* interface faster than 52 MHz, but defines maximum eMMC frequency as 200 MHz
* for proper divider settings.
*/
#define EMMC_SD_CLOCK_MIN 400000
#define EMMC_CLOCK_MAX 25000000
#define SD_CLOCK_MAX 52000000
static int cr50_irq_status(void)
{
return 0; /* FIXME - cannonlake_get_gpe(GPE0_DW1_12); *//* GPP_C12 */
}
static void zoombini_setup_tpm(void)
{
if (IS_ENABLED(CONFIG_DRIVER_TPM_SPI)) {
/* SPI TPM */
const IntelGspiSetupParams gspi0_params = {
.dev = PCI_DEV(0, 0x1e, 2),
.cs_polarity = SPI_POLARITY_LOW,
.clk_phase = SPI_CLOCK_PHASE_FIRST,
.clk_polarity = SPI_POLARITY_LOW,
.ref_clk_mhz = 120,
.gspi_clk_mhz = 1,
};
tpm_set_ops(&new_tpm_spi(new_intel_gspi(&gspi0_params),
cr50_irq_status)->ops);
} else if (IS_ENABLED(CONFIG_DRIVER_TPM_CR50_I2C)) {
DesignwareI2c *i2c1 = new_pci_designware_i2c(
PCI_DEV(0, 0x19, 1), 400000, CANNONLAKE_DW_I2C_MHZ);
tpm_set_ops(&new_cr50_i2c(&i2c1->ops, 0x50,
&cr50_irq_status)->base.ops);
}
}
static int board_setup(void)
{
sysinfo_install_flags(NULL);
/* TPM */
zoombini_setup_tpm();
/* Chrome EC (eSPI) */
CrosEcLpcBus *cros_ec_lpc_bus =
new_cros_ec_lpc_bus(CROS_EC_LPC_BUS_GENERIC);
CrosEc *cros_ec = new_cros_ec(&cros_ec_lpc_bus->ops, 0, NULL);
register_vboot_ec(&cros_ec->vboot, 0);
/* 16MB SPI Flash */
flash_set_ops(&new_mem_mapped_flash(0xff000000, 0x1000000)->ops);
/* PCH Power */
power_set_ops(&cannonlake_power_ops);
uintptr_t UsbMmioBase =
pci_read_config32(PCI_DEV(0, 0x14, 0), PCI_BASE_ADDRESS_0);
UsbMmioBase &= 0xFFFF0000; /* 32 bits only */
UsbHostController *usb_host1 = new_usb_hc(XHCI, UsbMmioBase);
list_insert_after(&usb_host1->list_node, &usb_host_controllers);
/* eMMC */
SdhciHost *emmc = new_pci_sdhci_host(PCI_DEV(0, 0x1a, 0), 0,
EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX);
list_insert_after(&emmc->mmc_ctrlr.ctrlr.list_node,
&fixed_block_dev_controllers);
/* SD Card (if present) */
pcidev_t sd_pci_dev = PCI_DEV(0, 0x14, 5);
uint16_t sd_vendor_id = pci_read_config32(sd_pci_dev, REG_VENDOR_ID);
if (sd_vendor_id == PCI_VENDOR_ID_INTEL) {
SdhciHost *sd = new_pci_sdhci_host(sd_pci_dev, 1,
EMMC_SD_CLOCK_MIN, SD_CLOCK_MAX);
list_insert_after(&sd->mmc_ctrlr.ctrlr.list_node,
&removable_block_dev_controllers);
}
return 0;
}
INIT_FUNC(board_setup);
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