Commit 4d7ff7b0 authored by Bora Guvendik's avatar Bora Guvendik Committed by chrome-bot

cnlrvp: add initial board support files

Add cnl rvp board and config files

BRANCH=None
BUG=None
TEST=Boot to OS via SATA/eMMC/USB on cnl-u rvp

Change-Id: I7c75e47f7d90a22ce34bb1b62d3b54a2eab71ad7
Signed-off-by: default avatarBora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/667873Reviewed-by: default avatarAaron Durbin <adurbin@chromium.org>
Reviewed-by: default avatarFurquan Shaikh <furquan@chromium.org>
Reviewed-by: default avatarNick Vaccaro <nvaccaro@chromium.org>
parent 2b506147
# Arch
CONFIG_ARCH_X86=y
# Board
CONFIG_BOARD="cnlrvp"
# Image
CONFIG_FMAP_OFFSET=0xC90000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=n
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_ACPI=y
CONFIG_NV_STORAGE_CMOS=y
# Kernel format
CONFIG_KERNEL_ZIMAGE=y
# Drivers
CONFIG_DRIVER_BUS_I2C_CROS_EC_TUNNEL=y
CONFIG_DRIVER_BUS_I2C_DESIGNWARE=y
CONFIG_DRIVER_BUS_I2C_DESIGNWARE_PCI=y
CONFIG_DRIVER_EC_CROS=n
CONFIG_DRIVER_EC_CROS_LPC=n
CONFIG_DRIVER_FLASH_MEMMAPPED=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
CONFIG_DRIVER_SOUND_GPIO_I2S=y
CONFIG_DRIVER_SOUND_GPIO_PDM=y
CONFIG_DRIVER_SOUND_MAX98357A=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_SOUND_SSM4567=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_SDHCI_PCI=y
CONFIG_DRIVER_AHCI=y
CONFIG_MOCK_TPM=y
depthcharge-y += board.c
/*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2016 Intel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* These needs to be included first.
* Some of the driver headers would be dependent on these.
*/
#include <pci.h>
#include <pci/pci.h>
#include "base/init_funcs.h"
#include "base/list.h"
#include "drivers/bus/i2c/designware.h"
#include "drivers/bus/i2c/i2c.h"
#include "drivers/bus/usb/usb.h"
#include "drivers/flash/flash.h"
#include "drivers/flash/memmapped.h"
#include "drivers/storage/ahci.h"
#include "drivers/gpio/sysinfo.h"
#include "drivers/power/pch.h"
#include "drivers/storage/blockdev.h"
#include "drivers/storage/sdhci.h"
#include "drivers/tpm/lpc.h"
#include "drivers/tpm/tpm.h"
#include <gbb_header.h>
#include <libpayload.h>
#include <sysinfo.h>
#include "vboot/util/flag.h"
#include "vboot/util/commonparams.h"
/*
* Clock frequencies for the eMMC and SD ports are defined below. The minimum
* frequency is the same for both interfaces, the firmware does not run any
* interface faster than 52 MHz, but defines maximum eMMC frequency as 200 MHz
* for proper divider settings.
*/
#define EMMC_SD_CLOCK_MIN 400000
#define EMMC_CLOCK_MAX 25000000
#define SD_CLOCK_MAX 52000000
static int board_setup(void)
{
sysinfo_install_flags(NULL);
/* 16MB SPI Flash */
flash_set_ops(&new_mem_mapped_flash(0xff000000, 0x1000000)->ops);
/* PCH Power */
power_set_ops(&cannonlake_power_ops);
uintptr_t UsbMmioBase =
pci_read_config32(PCI_DEV(0, 0x14, 0), PCI_BASE_ADDRESS_0);
UsbMmioBase &= 0xFFFF0000; /* 32 bits only */
UsbHostController *usb_host1 = new_usb_hc(XHCI, UsbMmioBase);
list_insert_after(&usb_host1->list_node, &usb_host_controllers);
/* SATA SSD */
AhciCtrlr *ahci = new_ahci_ctrlr(PCI_DEV(0, 0x17, 0));
list_insert_after(&ahci->ctrlr.list_node, &fixed_block_dev_controllers);
/* eMMC */
SdhciHost *emmc = new_pci_sdhci_host(PCI_DEV(0, 0x1a, 0), 0,
EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX);
list_insert_after(&emmc->mmc_ctrlr.ctrlr.list_node,
&fixed_block_dev_controllers);
return 0;
}
INIT_FUNC(board_setup);
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