Commit aacca183 authored by Marc Jones's avatar Marc Jones Committed by chrome-bot
Browse files

SDHCI: Clear transfer mode before CMD without data



Reference Linux Kernel patch commit ("9b8ffea6efb0")

    mmc: sdhci: Add a quirk for AMD SDHC transfer mode register
    need to be cleared for cmd without data

    SDHC controller in AMD chipsets require SDHC transfer mode
    register to be cleared for commands without data. The issue was
    uncovered during testing eMMC cards on KB/ML based platforms

BUG=b:63891719
BRANCH=none
TEST=Boot Kahlee onboard MMC.

Change-Id: I913e2fa77d1ef0d85510095aa2fac66484a191c5
Signed-off-by: default avatarMarc Jones <marcj303@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/584030


Commit-Ready: Marc Jones <marc.jones@scarletltd.com>
Tested-by: default avatarMarc Jones <marc.jones@scarletltd.com>
Reviewed-by: default avatarJulius Werner <jwerner@chromium.org>
parent bacd1db7
......@@ -344,6 +344,11 @@ static int sdhci_send_command_bounced(MmcCtrlr *mmc_ctrl, MmcCommand *cmd,
mode |= SDHCI_TRNS_DMA;
}
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
} else {
/* Quirk: Some AMD chipsets require the cleraring the
* transfer mode 0 before sending a command without data.
* Commands with data always set the transfer mode */
sdhci_writew(host, 0, SDHCI_TRANSFER_MODE);
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
......
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