Commit df92a81c authored by Stefan Reinauer's avatar Stefan Reinauer Committed by chrome-bot
Browse files

Drop boards without coreboot counterpart


Signed-off-by: default avatarStefan Reinauer <reinauer@google.com>

BRANCH=none
BUG=none
TEST=none, can't build working firmware for these anyways

Change-Id: I00078fc5001fffeb7e7844914a0675c308ad5cf0
Reviewed-on: https://chromium-review.googlesource.com/600639


Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Tested-by: default avatarStefan Reinauer <reinauer@chromium.org>
Reviewed-by: default avatarFurquan Shaikh <furquan@chromium.org>
parent a0ef2790
# Arch
CONFIG_ARCH_X86=y
# Board
CONFIG_BOARD="lars"
# Image
CONFIG_FMAP_OFFSET=0xc10000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_OPROM_MATTERS=y
CONFIG_CROSSYSTEM_ACPI=y
CONFIG_NV_STORAGE_CMOS=y
# Kernel format
CONFIG_KERNEL_ZIMAGE=y
# Drivers
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_LPC=y
CONFIG_DRIVER_FLASH_MEMMAPPED=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
CONFIG_DRIVER_SOC_SKYLAKE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_SDHCI_PCI=y
CONFIG_DRIVER_TPM_LPC=y
# Boot beep
CONFIG_DRIVER_SOUND_GPIO_I2S=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_SOUND_MAX98357A=y
# Arch
CONFIG_ARCH_ARM=y
# Board
CONFIG_BOARD="veyron_gus"
CONFIG_BOARD_DIR="veyron"
# Image
CONFIG_BASE_ADDRESS=0x43000000
CONFIG_FMAP_OFFSET=0x00100000
CONFIG_HEAP_SIZE=0x01000000
CONFIG_KERNEL_START=0x2000000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_FDT=y
CONFIG_NV_STORAGE_CROS_EC=y
#CONFIG_MOCK_TPM=y
# Kernel format
CONFIG_KERNEL_FIT=y
CONFIG_KERNEL_FIT_FDT_ADDR=0x6400000
# Drivers
CONFIG_DRIVER_GPIO_RK3288=y
CONFIG_DRIVER_BUS_I2C_ROCKCHIP=y
CONFIG_DRIVER_BUS_SPI_ROCKCHIP=y
CONFIG_DRIVER_BUS_I2S_ROCKCHIP=y
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_SPI=y
CONFIG_DRIVER_EC_CROS_SPI_WAKEUP_DELAY_US=100
CONFIG_DRIVER_FLASH_SPI=y
CONFIG_DRIVER_POWER_RK808=y
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_MKBP_OLD_COMMAND=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_SOUND_I2S=y
CONFIG_DRIVER_SOUND_MAX98090=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_DWMMC_RK3288=y
CONFIG_DRIVER_TPM_SLB9635_I2C=y
CONFIG_DRIVER_VIDEO_RK3288=y
# Arch
CONFIG_ARCH_ARM=y
# Board
CONFIG_BOARD="veyron_nicky"
CONFIG_BOARD_DIR="veyron"
# Image
CONFIG_BASE_ADDRESS=0x43000000
CONFIG_FMAP_OFFSET=0x00100000
CONFIG_HEAP_SIZE=0x01000000
CONFIG_KERNEL_START=0x2000000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_FDT=y
CONFIG_NV_STORAGE_CROS_EC=y
#CONFIG_MOCK_TPM=y
# Kernel format
CONFIG_KERNEL_FIT=y
CONFIG_KERNEL_FIT_FDT_ADDR=0x6400000
# Drivers
CONFIG_DRIVER_GPIO_RK3288=y
CONFIG_DRIVER_BUS_I2C_ROCKCHIP=y
CONFIG_DRIVER_BUS_SPI_ROCKCHIP=y
CONFIG_DRIVER_BUS_I2S_ROCKCHIP=y
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_SPI=y
CONFIG_DRIVER_EC_CROS_SPI_WAKEUP_DELAY_US=100
CONFIG_DRIVER_FLASH_SPI=y
CONFIG_DRIVER_POWER_RK808=y
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_MKBP_OLD_COMMAND=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_SOUND_I2S=y
CONFIG_DRIVER_SOUND_MAX98090=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_DWMMC_RK3288=y
CONFIG_DRIVER_TPM_SLB9635_I2C=y
CONFIG_DRIVER_VIDEO_RK3288=y
# Arch
CONFIG_ARCH_ARM=y
# Board
CONFIG_BOARD="veyron_pinky"
CONFIG_BOARD_DIR="veyron"
# Image
CONFIG_BASE_ADDRESS=0x43000000
CONFIG_FMAP_OFFSET=0x00100000
CONFIG_HEAP_SIZE=0x01000000
CONFIG_KERNEL_START=0x2000000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_FDT=y
CONFIG_NV_STORAGE_CROS_EC=y
#CONFIG_MOCK_TPM=y
# Kernel format
CONFIG_KERNEL_FIT=y
CONFIG_KERNEL_FIT_FDT_ADDR=0x6400000
# Drivers
CONFIG_DRIVER_GPIO_RK3288=y
CONFIG_DRIVER_BUS_I2C_ROCKCHIP=y
CONFIG_DRIVER_BUS_SPI_ROCKCHIP=y
CONFIG_DRIVER_BUS_I2S_ROCKCHIP=y
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_SPI=y
CONFIG_DRIVER_EC_CROS_SPI_WAKEUP_DELAY_US=100
CONFIG_DRIVER_FLASH_SPI=y
CONFIG_DRIVER_POWER_RK808=y
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_MKBP_OLD_COMMAND=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_SOUND_I2S=y
CONFIG_DRIVER_SOUND_MAX98090=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_DWMMC_RK3288=y
CONFIG_DRIVER_TPM_SLB9635_I2C=y
CONFIG_DRIVER_VIDEO_RK3288=y
# Arch
CONFIG_ARCH_ARM=y
# Board
CONFIG_BOARD="veyron_shark"
CONFIG_BOARD_DIR="veyron_shark"
# Boot
CONFIG_ANDROID_DT_FIXUP=y
# Image
CONFIG_BASE_ADDRESS=0x43000000
CONFIG_FMAP_OFFSET=0x00100000
CONFIG_HEAP_SIZE=0x01000000
CONFIG_KERNEL_START=0x2000000
CONFIG_KERNEL_SIZE=0x8000000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_FDT=y
CONFIG_NV_STORAGE_CROS_EC=y
#CONFIG_MOCK_TPM=y
# Kernel format
CONFIG_KERNEL_FIT=y
CONFIG_KERNEL_FIT_FDT_ADDR=0x6400000
# Drivers
CONFIG_DRIVER_GPIO_RK3288=y
CONFIG_DRIVER_BUS_I2C_ROCKCHIP=y
CONFIG_DRIVER_BUS_SPI_ROCKCHIP=y
CONFIG_DRIVER_BUS_I2S_ROCKCHIP=y
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_SPI=y
CONFIG_DRIVER_EC_CROS_SPI_WAKEUP_DELAY_US=100
CONFIG_DRIVER_FLASH_SPI=y
CONFIG_DRIVER_POWER_RK808=y
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_MKBP_OLD_COMMAND=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_SOUND_I2S=y
CONFIG_DRIVER_SOUND_MAX98090=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_DWMMC_RK3288=y
CONFIG_DRIVER_TPM_SLB9635_I2C=y
CONFIG_DRIVER_VIDEO_RK3288=y
# Fastboot
CONFIG_FASTBOOT_MODE=y
CONFIG_FASTBOOT_USBVID=0x18d1
CONFIG_FASTBOOT_USBDID=0x4e30
CONFIG_FASTBOOT_EP_IN=8
CONFIG_FASTBOOT_EP_OUT=8
# Arch
CONFIG_ARCH_ARM=y
# Board
CONFIG_BOARD="veyron_thea"
CONFIG_BOARD_DIR="veyron"
# Image
CONFIG_BASE_ADDRESS=0x43000000
CONFIG_FMAP_OFFSET=0x00100000
CONFIG_HEAP_SIZE=0x01000000
CONFIG_KERNEL_START=0x2000000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_CROSSYSTEM_FDT=y
CONFIG_NV_STORAGE_CROS_EC=y
#CONFIG_MOCK_TPM=y
# Kernel format
CONFIG_KERNEL_FIT=y
CONFIG_KERNEL_FIT_FDT_ADDR=0x6400000
# Drivers
CONFIG_DRIVER_GPIO_RK3288=y
CONFIG_DRIVER_BUS_I2C_ROCKCHIP=y
CONFIG_DRIVER_BUS_SPI_ROCKCHIP=y
CONFIG_DRIVER_BUS_I2S_ROCKCHIP=y
CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_SPI=y
CONFIG_DRIVER_EC_CROS_SPI_WAKEUP_DELAY_US=100
CONFIG_DRIVER_FLASH_SPI=y
CONFIG_DRIVER_POWER_RK808=y
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_MKBP_OLD_COMMAND=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_SOUND_I2S=y
CONFIG_DRIVER_SOUND_MAX98090=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_DWMMC_RK3288=y
CONFIG_DRIVER_TPM_SLB9635_I2C=y
CONFIG_DRIVER_VIDEO_RK3288=y
##
## Copyright 2013 Google Inc. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## Copyright 2013 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
depthcharge-y += board.c
/*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <pci.h>
#include <pci/pci.h>
#include <libpayload.h>
#include <sysinfo.h>
#include "base/init_funcs.h"
#include "base/list.h"
#include "drivers/ec/cros/lpc.h"
#include "drivers/flash/flash.h"
#include "drivers/flash/memmapped.h"
#include "drivers/gpio/skylake.h"
#include "drivers/gpio/sysinfo.h"
#include "drivers/power/pch.h"
#include "drivers/sound/gpio_i2s.h"
#include "drivers/sound/max98357a.h"
#include "drivers/sound/route.h"
#include "drivers/storage/blockdev.h"
#include "drivers/storage/sdhci.h"
#include "drivers/tpm/lpc.h"
#include "drivers/tpm/tpm.h"
#include "vboot/util/flag.h"
#include "drivers/bus/usb/usb.h"
/*
* Clock frequencies for the eMMC and SD ports are defined below. The minimum
* frequency is the same for both interfaces, the firmware does not run any
* interface faster than 52 MHz, but defines maximum eMMC frequency as 200 MHz
* for proper divider settings.
*/
#define EMMC_SD_CLOCK_MIN 400000
#define EMMC_CLOCK_MAX 200000000
static int board_setup(void)
{
sysinfo_install_flags(new_skylake_gpio_input_from_coreboot);
/* MEC1322 Chrome EC */
CrosEcLpcBus *cros_ec_lpc_bus =
new_cros_ec_lpc_bus(CROS_EC_LPC_BUS_MEC);
CrosEc *cros_ec = new_cros_ec(&cros_ec_lpc_bus->ops, 0, NULL);
CrosEc *cros_pd = new_cros_ec(&cros_ec_lpc_bus->ops, 1, NULL);
register_vboot_ec(&cros_ec->vboot, 0);
register_vboot_ec(&cros_pd->vboot, 1);
/* 16MB SPI Flash */
flash_set_ops(&new_mem_mapped_flash(0xff000000, 0x1000000)->ops);
/* SPI TPM memory mapped to act like LPC TPM */
tpm_set_ops(&new_lpc_tpm((void *)(uintptr_t)0xfed40000)->ops);
/* PCH Power */
power_set_ops(&skylake_power_ops);
/* eMMC */
SdhciHost *emmc = new_pci_sdhci_host(PCI_DEV(0, 0x1e, 4),
SDHCI_PLATFORM_NO_EMMC_HS200,
EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX);
list_insert_after(&emmc->mmc_ctrlr.ctrlr.list_node,
&fixed_block_dev_controllers);
/* Speaker Amp codec MAX98357A */
GpioOps *sdmode_gpio = &new_skylake_gpio_output(GPP_B2, 0)->ops;
max98357aCodec *speaker_amp =
new_max98357a_codec(sdmode_gpio);
/* GPIO to activate buffer to isolate I2S from PCH & allow GPIO */
GpioCfg *boot_beep_gpio_cfg = new_skylake_gpio_output(GPP_F23, 0);
gpio_set(&boot_beep_gpio_cfg->ops, 1);
/* Use GPIO to bit-bang I2S to the codec */
GpioCfg *i2s2_bclk = new_skylake_gpio_output(GPP_F0, 0);
GpioCfg *i2s2_sfrm = new_skylake_gpio_output(GPP_F1, 0);
GpioCfg *i2s2_txd = new_skylake_gpio_output(GPP_F2, 0);
GpioI2s *i2s = new_gpio_i2s(
&i2s2_bclk->ops, /* I2S Bit Clock GPIO */
&i2s2_sfrm->ops, /* I2S Frame Sync GPIO */
&i2s2_txd->ops, /* I2S Data GPIO */
16000, /* Sample rate */
2, /* Channels */
0x1FFF); /* Volume */
/* Connect the Codec to the I2S source */
SoundRoute *sound = new_sound_route(&i2s->ops);
list_insert_after(&speaker_amp->component.list_node,
&sound->components);
sound_set_ops(&sound->ops);
return 0;
}
INIT_FUNC(board_setup);
##
##
## Copyright 2014 Rockchip Electronics Co., Ltd.
## Copyright 2015 Google Inc
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
depthcharge-y += board.c
fastboot-y += fastboot.c
/*
* Copyright 2014 Rockchip Electronics Co., Ltd.
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include "base/init_funcs.h"
#include "board/veyron_shark/fastboot.h"
#include "boot/fit.h"
#include "drivers/bus/i2c/rockchip.h"
#include "drivers/bus/i2s/rockchip.h"
#include "drivers/bus/spi/rockchip.h"
#include "drivers/bus/usb/usb.h"
#include "drivers/ec/cros/spi.h"
#include "drivers/flash/block_flash.h"
#include "drivers/flash/spi.h"
#include "drivers/gpio/rockchip.h"
#include "drivers/gpio/sysinfo.h"
#include "drivers/power/rk808.h"
#include "drivers/power/sysinfo.h"
#include "drivers/storage/dw_mmc.h"
#include "drivers/storage/rk_dwmmc.h"
#include "drivers/sound/i2s.h"
#include "drivers/sound/route.h"
#include "drivers/sound/max98090.h"
#include "drivers/tpm/slb9635_i2c.h"
#include "drivers/tpm/tpm.h"
#include "drivers/video/display.h"
#include "drivers/video/rk3288.h"
#include "vboot/boot_policy.h"
#include "vboot/util/flag.h"
void __attribute__((weak))
fill_fb_info(BlockDevCtrlr *bdev_ctrlr_arr[BDEV_COUNT])
{
/* Default weak implementation. */
}
const char *hardware_name(void)
{
return "shark";
}
static int board_setup(void)
{
static const struct boot_policy policy[] = {
{KERNEL_IMAGE_BOOTIMG, CMD_LINE_BOOTIMG_HDR},
{KERNEL_IMAGE_CROS, CMD_LINE_SIGNER},
};
if (set_boot_policy(policy, ARRAY_SIZE(policy)) == -1)
halt();
RkSpi *spi2 = new_rockchip_spi(0xff130000);
SpiFlash *flash = new_spi_flash(&spi2->ops);
flash_set_ops(&flash->ops);
FlashBlockDev *fbdev = block_flash_register_nor(&flash->ops);
RkSpi *spi0 = new_rockchip_spi(0xff110000);
CrosEcSpiBus *cros_ec_spi_bus = new_cros_ec_spi_bus(&spi0->ops);
GpioOps *ec_int = sysinfo_lookup_gpio("EC interrupt", 1,
new_rk_gpio_input_from_coreboot);
CrosEc *cros_ec = new_cros_ec(&cros_ec_spi_bus->ops, 0, ec_int);
register_vboot_ec(&cros_ec->vboot, 0);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
RkI2c *i2c1 = new_rockchip_i2c((void *)0xff140000);
tpm_set_ops(&new_slb9635_i2c(&i2c1->ops, 0x20)->base.ops);
RockchipI2s *i2s0 = new_rockchip_i2s(0xff890000, 16, 2, 256);
I2sSource *i2s_source = new_i2s_source(&i2s0->ops, 48000, 2, 16000);
SoundRoute *sound_route = new_sound_route(&i2s_source->ops);
RkI2c *i2c2 = new_rockchip_i2c((void *)0xff660000);
Max98090Codec *codec = new_max98090_codec(&i2c2->ops, 0x10, 16, 48000,
256, 1);
list_insert_after(&codec->component.list_node,
&sound_route->components);
sound_set_ops(&sound_route->ops);
RkI2c *i2c0 = new_rockchip_i2c((void *)0xff650000);
Rk808Pmic *pmic = new_rk808_pmic(&i2c0->ops, 0x1b);
SysinfoResetPowerOps *power = new_sysinfo_reset_power_ops(&pmic->ops,
new_rk_gpio_output_from_coreboot);
power_set_ops(&power->ops);
DwmciHost *emmc = new_rkdwmci_host(0xff0f0000, 594000000, 8, 0, NULL);
list_insert_after(&emmc->mmc.ctrlr.list_node,
&fixed_block_dev_controllers);
RkGpio *card_detect = new_rk_gpio_input(GPIO(7, A, 5));
GpioOps *card_detect_ops = &card_detect->ops;
card_detect_ops = new_gpio_not(card_detect_ops);
DwmciHost *sd_card = new_rkdwmci_host(0xff0c0000, 594000000, 4, 1,
card_detect_ops);
list_insert_after(&sd_card->mmc.ctrlr.list_node,
&removable_block_dev_controllers);
UsbHostController *usb_host1 = new_usb_hc(DWC2, 0xff540000);
list_insert_after(&usb_host1->list_node, &usb_host_controllers);
UsbHostController *usb_otg = new_usb_hc(DWC2, 0xff580000);
list_insert_after(&usb_otg->list_node, &usb_host_controllers);
if (lib_sysinfo.framebuffer != NULL) {
GpioOps *backlight_gpio = sysinfo_lookup_gpio("backlight", 1,
new_rk_gpio_output_from_coreboot);
display_set_ops(new_rk3288_display(backlight_gpio));
}
/* Fill in fastboot related information */
BlockDevCtrlr *bdev_arr[BDEV_COUNT] = {
[FLASH_BDEV] = &fbdev->ctrlr,
[MMC_BDEV] = &emmc->mmc.ctrlr,
};
fill_fb_info(bdev_arr);
return 0;
}
INIT_FUNC(board_setup);
/*
* Copyright 2015 Google Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <libpayload.h>
#include <udc/dwc2_udc.h>
#include "board/veyron_shark/fastboot.h"
#include "config.h"
#include "drivers/bus/usb/usb.h"
#include "image/fmap.h"
#include "vboot/firmware_id.h"
struct bdev_info fb_bdev_list[BDEV_COUNT] = {
[MMC_BDEV] = {"mmc", NULL, NULL},
[FLASH_BDEV] = {"flash", NULL, NULL},
};
size_t fb_bdev_count = ARRAY_SIZE(fb_bdev_list);
struct part_info fb_part_list[] = {
PART_NONGPT("chromeos", NULL, BDEV_ENTRY(MMC_BDEV), 0, 0),
PART_NONGPT("mbr", NULL, BDEV_ENTRY(MMC_BDEV), 0, 1),