1. 25 Sep, 2017 1 commit
  2. 22 Sep, 2017 1 commit
  3. 21 Sep, 2017 2 commits
  4. 13 Sep, 2017 1 commit
  5. 09 Sep, 2017 4 commits
  6. 08 Sep, 2017 1 commit
  7. 07 Sep, 2017 4 commits
  8. 29 Aug, 2017 1 commit
  9. 25 Aug, 2017 1 commit
  10. 22 Aug, 2017 2 commits
  11. 19 Aug, 2017 2 commits
  12. 18 Aug, 2017 2 commits
    • Caveh Jalali's avatar
      TCPC: use EC_CMD_PD_CHIP_INFO for TCPC info · e45c8083
      Caveh Jalali authored
      we have a dedicated EC command to get the TCPC version info - no need
      to directly scrape the regs.  this can also be used to force the EC to
      refresh its view (cache) of the TCPC version after a firmware update,
      so this is a good thing all around.
      i'm also removing dependencies on PD_SUSPEND and EC I2C tunneling in
      the *_check_hash() flow so this can work even when we have
      addresses the case where the AP does a soft reboot without affecting
      the EC.
      TEST=verified TCPC firmware update works as before.
      Change-Id: Ia64c93bfda50dd5a651836224b9fb9f6ce1db57c
      Signed-off-by: default avatarCaveh Jalali <caveh@google.com>
      Reviewed-on: https://chromium-review.googlesource.com/615089
      Reviewed-by: default avatarJulius Werner <jwerner@chromium.org>
    • Daisuke Nojiri's avatar
      crosEC: Do not add padding when writing to flash · 42f2d0c4
      Daisuke Nojiri authored
      When Depthcharge writes to flash through EC, it adds padding to make
      the data size equal to write_block_size of the SPI flash. Though this
      might be necessary for a certain board (Pit as described in CL:62895),
      this fails if we're writing to the end of the SPI flash because EC
      checks whether (offset + size) exceeds the flash size or not
      I think we should play this trick (padding to write block size) on the
      EC side. That is, if EC receives a short packet, it should add padding
      by itself if it's required.
      Pit has been removed from the crosEC tree. If this patch breaks another
      board, we'll fix it differently (as suggested above).
      TEST=Let Depthcharge on Fizz write a RW image to the slot B, which is
      located at the end.
      Change-Id: I2f51917976189ea01de8c5787f6329f0a45c7f74
      Signed-off-by: default avatarDaisuke Nojiri <dnojiri@chromium.org>
      Reviewed-on: https://chromium-review.googlesource.com/618164
      Reviewed-by: default avatarAaron Durbin <adurbin@chromium.org>
      Reviewed-by: default avatarRandall Spangler <rspangler@chromium.org>
  13. 17 Aug, 2017 1 commit
  14. 16 Aug, 2017 1 commit
  15. 15 Aug, 2017 2 commits
    • Caveh Jalali's avatar
      anx3429: FW update driver. · 8d3cfc6d
      Caveh Jalali authored
      this driver adds the capability to update the firmware of the anx3429
      TCPC.  the driver will be registered with vboot to be invoked during
      software sync, much like the ps8751 TCPC update driver.
      TEST=in conjunction with follow-on CLs, verified we can update the
      	OTP.  for now, only tested with a test pattern being
      	programmed into an unused area of the OTP ROM.
      Change-Id: I518aa4f9408bcaf624278685015d91395fad43f6
      Signed-off-by: default avatarCaveh Jalali <caveh@google.com>
      Reviewed-on: https://chromium-review.googlesource.com/592641
    • Shelley Chen's avatar
      detachables: Disable "Enable Developer Mode" entry in Recovery Menu · 7a72ea10
      Shelley Chen authored
      Remove "Enable Developer Mode" entry in Recovery Menu when board is
      already in developer mode.  Having the entry present was confusing
      users trying to enable dev mode when machine already in dev mode and
      seeing nothing happen.  Changing VbExDisplayMenu API so that a
      disabled_idx_mask is passed down to allow for the general
      disabling/enabling of menu items.
      BUG=b:63078243, b:35585623
      TEST=reboot into recovery with DUT already in dev mode.  Make sure
           Enable Developer Mode entry is not displayed.
           reboot into recovery with DUT in normal mode.  Make sure
           Enable Developer Mode entry is displayed and can be selected.
      Change-Id: I70f07acd740169e077d19148f70e66f9c78bd520
      Signed-off-by: default avatarShelley Chen <shchen@chromium.org>
      Reviewed-on: https://chromium-review.googlesource.com/565335
      Reviewed-by: default avatarJulius Werner <jwerner@chromium.org>
  16. 09 Aug, 2017 4 commits
  17. 08 Aug, 2017 2 commits
  18. 05 Aug, 2017 1 commit
  19. 03 Aug, 2017 1 commit
  20. 02 Aug, 2017 2 commits
  21. 01 Aug, 2017 2 commits
  22. 30 Jul, 2017 1 commit
    • Furquan Shaikh's avatar
      i2c/designware: Do not re-initialize bus if configured by coreboot · 9ee4a955
      Furquan Shaikh authored
      Coreboot is taking a lot of effort reading device-tree values for
      fall/rise time or lcnt/hcnt and calculating and configuring
      controller register values to ensure I2C bus speed is within limits
      when used in firmware. Depthcharge driver was resetting all those
      values by using default configuration. This resulted in I2C bus speed
      in depthcharge going beyond limits. (Noticed by sudden spike in H1 I2C
      frequency in depthcharge).
      This change updates the designware I2C driver to check if high and low
      cycle time registers are already configured and skip initialization
      of the bus completely.
      TEST=Verified that H1 I2C frequency is <400KHz in coreboot and in
      depthcharge. No spikes observed after jumping to depthcharge. Also, no
      errors seen while communicating with H1 in depthcharge.
      Change-Id: Icc2d2d45710a203325d1780f80e2e8d024c8c9a4
      Signed-off-by: default avatarFurquan Shaikh <furquan@chromium.org>
      Reviewed-on: https://chromium-review.googlesource.com/592550
      Reviewed-by: default avatarDuncan Laurie <dlaurie@google.com>
  23. 21 Jul, 2017 1 commit