clk: Exynos: Add all APLL/RPLL/VPLL clocks

Synchronise the APLL/RPLL/VPLL clock tables for 542x variants with the
chromeos-3.8 tree. This adds 2.1GHz to APLL for 5422/5800, as well as
the full suite of RPLL/VPLL clocks. For both of RPLL/VPLL, 5422/5800
support one additional clock over 5420.

Additionally, restrict KPLL to 1.5GHz maximum.

Signed-off-by: Daniel Stone <daniels@collabora.com>

drivers/clk/samsung/clk-exynos5420.c

@@ -1200,6 +1200,42 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
 	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
 };
 
+/* For both VPLL and RPLL, 5422/5800 support one extra clock (543MHz on VPLL,
+ * and 150MHz on RPLL) compared to 5420. */
+static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
+	PLL_35XX_RATE(600000000, 200, 2, 2),
+	PLL_35XX_RATE(543000000, 181, 2, 2),
+	PLL_35XX_RATE(533000000, 266, 3, 2),
+	PLL_35XX_RATE(480000000, 320, 4, 2),
+	PLL_35XX_RATE(420000000, 140, 2, 2),
+	PLL_35XX_RATE(350000000, 175, 3, 2),
+	PLL_35XX_RATE(266000000, 266, 3, 3),
+	PLL_35XX_RATE(177000000, 118, 2, 3),
+	PLL_35XX_RATE(100000000, 200, 3, 4),
+};
+
+static const struct samsung_pll_rate_table exynos5422_vpll_24mhz_tbl[] = {
+	PLL_35XX_RATE(600000000, 200, 2, 2),
+	PLL_35XX_RATE(533000000, 266, 3, 2),
+	PLL_35XX_RATE(480000000, 320, 4, 2),
+	PLL_35XX_RATE(420000000, 140, 2, 2),
+	PLL_35XX_RATE(350000000, 175, 3, 2),
+	PLL_35XX_RATE(266000000, 266, 3, 3),
+	PLL_35XX_RATE(177000000, 118, 2, 3),
+	PLL_35XX_RATE(100000000, 200, 3, 4),
+};
+
+static const struct samsung_pll_rate_table exynos5420_rpll_24mhz_tbl[] = {
+	PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+	PLL_36XX_RATE(70500000, 95, 2, 4, 0),
+};
+
+static const struct samsung_pll_rate_table exynos5422_rpll_24mhz_tbl[] = {
+	PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+	PLL_36XX_RATE(150000000, 150, 3, 3, 0),
+	PLL_36XX_RATE(70500000, 95, 2, 4, 0),
+};
+
 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
 	PLL_35XX_RATE(2000000000, 250, 3, 0),
 	PLL_35XX_RATE(1900000000, 475, 6, 0),
@@ -1279,6 +1315,14 @@ static void __init exynos5x_clk_init(struct device_node *np,
 	if (_get_rate("fin_pll") == 24 * MHZ) {
 		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+
+		if (soc == EXYNOS5420) {
+			exynos5x_plls[rpll].rate_table = exynos5420_vpll_24mhz_tbl;
+			exynos5x_plls[rpll].rate_table = exynos5420_rpll_24mhz_tbl;
+		} else {
+			exynos5x_plls[vpll].rate_table = exynos5422_vpll_24mhz_tbl;
+			exynos5x_plls[rpll].rate_table = exynos5422_rpll_24mhz_tbl;
+		}
 	}
 
 	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),