From 0765d9b09dc65b632c226b13b147418395c8afb0 Mon Sep 17 00:00:00 2001 From: Sugar Zhang <sugar.zhang@rock-chips.com> Date: Mon, 23 Sep 2024 18:10:37 +0800 Subject: [PATCH] rockchip: rk3588: Set DMAC0 QoS for 0x404 set DMAC0 to priority 0x404 to keep the same with DMAC1/2 which had been set 0x404 by default. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I752c03a0b7d1026fe852965b13f65b789e14ab27 --- arch/arm/mach-rockchip/rk3588/rk3588.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 2d3d83033f9..cad2c2e6813 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -95,6 +95,7 @@ DECLARE_GLOBAL_DATA_PTR; #define HDMIRX_NODE_FDT_PATH "/hdmirx-controller@fdee0000" #define RK3588_PHY_CONFIG 0xfdee00c0 +#define DMAC0_PRIORITY_REG 0xfdf32208 #define VOP_M0_PRIORITY_REG 0xfdf82008 #define VOP_M1_PRIORITY_REG 0xfdf82208 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7)) @@ -1045,6 +1046,12 @@ int arch_cpu_init(void) writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L); writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H); #endif + /* + * set DMAC0 to priority 0x404 to keep the same with DMAC1/2 + * which had been set 0x404 by default. + */ + writel(QOS_PRIORITY_LEVEL(4, 4), DMAC0_PRIORITY_REG); + /* * set VOP M0 and VOP M1 to priority 0x303,then * Peri > VOP/MCU > ISP/VICAP > other -- GitLab