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Commit 4ca06607 authored by Haiying Wang's avatar Haiying Wang Committed by Wolfgang Denk
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Add ddr interleaving suppport for MPC8572DS board


* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.

* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.

Signed-off-by: default avatarJames Yang <James.Yang@freescale.com>
Signed-off-by: default avatarHaiying Wang <Haiying.Wang@freescale.com>
parent 1f293b41
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