Skip to content
Snippets Groups Projects
Commit 59d63f7d authored by Stephen Warren's avatar Stephen Warren Committed by Tom Rini
Browse files

ARM: arm1176: Define arch_cpu_init() at the SoC level


Commit 86c63265 "ARM: arm1176: enable instruction cache in
arch_cpu_init()" defined arch_cpu_init() in a file that is shared across
all arm1176 SoCs. tnetv107x already implemented this function, which
caused linking to break. Move the new conflicting arch_cpu_init() into
arm1176/bcm2835/init.c so that it doesn't conflict; grep indicates this
function is usually defined at the SoC-level, not the CPU-level, at least
for ARM.

Signed-off-by: default avatarStephen Warren <swarren@wwwdotorg.org>
Acked-by: default avatarMarek Vasut <marex@denx.de>
parent 5675b509
No related merge requests found
......@@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
COBJS := reset.o timer.o
COBJS := init.o reset.o timer.o
SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
......
/*
* (C) Copyright 2012 Stephen Warren
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
int arch_cpu_init(void)
{
icache_enable();
return 0;
}
......@@ -65,10 +65,3 @@ static void cache_flush (void)
/* mem barrier to sync things */
asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
}
int arch_cpu_init(void)
{
icache_enable();
return 0;
}
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment