diff --git a/Makefile b/Makefile
index 43b57da325e3f12aec29d4600f094e877c776930..4a630a5562475dabd9199431f1667a57dacbd2c3 100644
--- a/Makefile
+++ b/Makefile
@@ -102,10 +102,11 @@ endif # ifneq ($(BUILD_DIR),)
OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
SPLTREE := $(OBJTREE)/spl
+TPLTREE := $(OBJTREE)/tpl
SRCTREE := $(CURDIR)
TOPDIR := $(SRCTREE)
LNDIR := $(OBJTREE)
-export TOPDIR SRCTREE OBJTREE SPLTREE
+export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
MKCONFIG := $(SRCTREE)/mkconfig
export MKCONFIG
@@ -397,6 +398,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
@@ -475,13 +477,25 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
+# $@ is output, $(1) and $(2) are inputs, $(3) is padded intermediate,
+# $(4) is pad-to
+SPL_PAD_APPEND = \
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(4) -I binary -O binary \
+ $(1) $(obj)$(3); \
+ cat $(obj)$(3) $(2) > $@; \
+ rm $(obj)$(3)
+ifdef CONFIG_TPL
+SPL_PAYLOAD := $(obj)tpl/u-boot-with-tpl.bin
+else
+SPL_PAYLOAD := $(obj)u-boot.bin
+endif
-$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
- -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
- rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD)
+ $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO))
+
+$(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin
+ $(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO))
$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
@@ -607,6 +621,9 @@ $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all
+$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
+ $(MAKE) -C spl all CONFIG_TPL_BUILD=y
+
updater:
$(MAKE) -C tools/updater all
@@ -614,6 +631,7 @@ updater:
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
$(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk \
$(obj)include/autoconf.mk \
$(obj)include/generated/generic-asm-offsets.h \
$(obj)include/generated/asm-offsets.h
@@ -696,6 +714,15 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
mv $@.tmp $@
# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
+$(obj)include/tpl-autoconf.mk: $(obj)include/config.h
+ @$(XECHO) Generating $@ ; \
+ set -e ; \
+ : Extract the config macros ; \
+ $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\
+ -DDO_DEPS_ONLY -dM include/common.h | \
+ sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
+ mv $@.tmp $@
+
$(obj)include/spl-autoconf.mk: $(obj)include/config.h
@$(XECHO) Generating $@ ; \
set -e ; \
@@ -706,12 +733,14 @@ $(obj)include/spl-autoconf.mk: $(obj)include/config.h
$(obj)include/generated/generic-asm-offsets.h: $(obj)include/autoconf.mk.dep \
$(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk \
$(obj)lib/asm-offsets.s
@$(XECHO) Generating $@
tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@
$(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \
$(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk \
$(src)lib/asm-offsets.c
@mkdir -p $(obj)lib
$(CC) -DDO_DEPS_ONLY \
@@ -720,12 +749,14 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \
$(obj)include/generated/asm-offsets.h: $(obj)include/autoconf.mk.dep \
$(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk \
$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@$(XECHO) Generating $@
tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@
$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/autoconf.mk.dep \
- $(obj)include/spl-autoconf.mk
+ $(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk
@mkdir -p $(obj)$(CPUDIR)/$(SOC)
if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \
$(CC) -DDO_DEPS_ONLY \
@@ -798,7 +829,8 @@ unconfig:
@rm -f $(obj)include/config.h $(obj)include/config.mk \
$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \
$(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \
- $(obj)include/spl-autoconf.mk
+ $(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk
%_config:: unconfig
@$(MKCONFIG) -A $(@:_config=)
@@ -884,6 +916,8 @@ clobber: tidy
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/u-boot-spl.lds
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map}
+ @rm -f $(obj)tpl/u-boot-spl.lds
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
diff --git a/README b/README
index 953ff179006dcf6bd3913657335469cc66c17019..677c3dc252174f62dacc13bb93ab4aad702e63a6 100644
--- a/README
+++ b/README
@@ -3090,6 +3090,14 @@ FIT uImage format:
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
+ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+ Set for the SPL on PPC mpc8xxx targets, support for
+ arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+
+ CONFIG_SPL_COMMON_INIT_DDR
+ Set for common ddr init with serial presence detect in
+ SPL binary.
+
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -3159,6 +3167,17 @@ FIT uImage format:
option to re-enable it. This will affect the output of the
bootm command when booting a FIT image.
+- TPL framework
+ CONFIG_TPL
+ Enable building of TPL globally.
+
+ CONFIG_TPL_PAD_TO
+ Image offset to which the TPL should be padded before appending
+ the TPL payload. By default, this is defined as
+ CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+ CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+ payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
+
Modem Support:
--------------
@@ -4196,6 +4215,11 @@ Low Level (hardware related) configuration options:
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+- CONFIG_TPL_BUILD
+ Modifies the behaviour of start.S when compiling a loader
+ that is executed after the SPL and before the actual U-Boot.
+ It is loaded by the SPL.
+
- CONFIG_SYS_MPC85XX_NO_RESETVEC
Only for 85xx systems. If this variable is specified, the section
.resetvec is not kept and the section .bootpg is placed in the
diff --git a/arch/powerpc/cpu/mpc824x/cpu.c b/arch/powerpc/cpu/mpc824x/cpu.c
index ee69e495b72d788c1f53fe94e3a662dd21122e1d..eaa4e87070b7f95b3020dc69816a2a54eb8b6491 100644
--- a/arch/powerpc/cpu/mpc824x/cpu.c
+++ b/arch/powerpc/cpu/mpc824x/cpu.c
@@ -45,12 +45,10 @@ int checkcpu (void)
return -1; /* no valid CPU revision info */
}
- printf (" at %s MHz:", strmhz (buf, clock));
+ printf(" at %s MHz: ", strmhz(buf, clock));
- printf (" %u kB I-Cache", checkicache () >> 10);
- printf (" %u kB D-Cache", checkdcache () >> 10);
-
- puts ("\n");
+ print_size(checkicache(), " I-Cache ");
+ print_size(checkdcache(), " D-Cache\n");
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 05436f9947200cfee0cac078358a1215fb4ff467..eea264b15178f2d11436251ce81957cc74eff7a4 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -245,6 +245,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
+ if (IS_SVR_REV(svr, 1, 0))
+ puts("Work-around for Erratum A003571 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
puts("Work-around for Erratum A-005812 enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 66bc6a2ea362725f25a9bdedc131a7a98fec1dc8..1a0196c7c421db4924c9531c55574b4b467696af 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -135,81 +135,82 @@ int checkcpu (void)
if (!(i & 3))
printf ("\n ");
printf("CPU%d:%-4s MHz, ", core,
- strmhz(buf1, sysinfo.freqProcessor[core]));
+ strmhz(buf1, sysinfo.freq_processor[core]));
}
- printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+ printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
+ printf("\n");
#ifdef CONFIG_FSL_CORENET
if (ddr_sync == 1) {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
- strmhz(buf1, sysinfo.freqDDRBus/2),
- strmhz(buf2, sysinfo.freqDDRBus));
+ strmhz(buf1, sysinfo.freq_ddrbus/2),
+ strmhz(buf2, sysinfo.freq_ddrbus));
} else {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
- strmhz(buf1, sysinfo.freqDDRBus/2),
- strmhz(buf2, sysinfo.freqDDRBus));
+ strmhz(buf1, sysinfo.freq_ddrbus/2),
+ strmhz(buf2, sysinfo.freq_ddrbus));
}
#else
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
- strmhz(buf1, sysinfo.freqDDRBus/2),
- strmhz(buf2, sysinfo.freqDDRBus));
+ strmhz(buf1, sysinfo.freq_ddrbus/2),
+ strmhz(buf2, sysinfo.freq_ddrbus));
break;
case 0x7:
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
- strmhz(buf1, sysinfo.freqDDRBus/2),
- strmhz(buf2, sysinfo.freqDDRBus));
+ strmhz(buf1, sysinfo.freq_ddrbus/2),
+ strmhz(buf2, sysinfo.freq_ddrbus));
break;
default:
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
- strmhz(buf1, sysinfo.freqDDRBus/2),
- strmhz(buf2, sysinfo.freqDDRBus));
+ strmhz(buf1, sysinfo.freq_ddrbus/2),
+ strmhz(buf2, sysinfo.freq_ddrbus));
break;
}
#endif
#if defined(CONFIG_FSL_LBC)
- if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
- printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+ if (sysinfo.freq_localbus > LCRR_CLKDIV) {
+ printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
- sysinfo.freqLocalBus);
+ sysinfo.freq_localbus);
}
#endif
#if defined(CONFIG_FSL_IFC)
- printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+ printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
#endif
#ifdef CONFIG_CPM2
- printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
+ printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
#endif
#ifdef CONFIG_QE
- printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
+ printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
- strmhz(buf1, sysinfo.freqFMan[i]));
+ strmhz(buf1, sysinfo.freq_fman[i]));
}
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+ printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
#endif
#ifdef CONFIG_SYS_DPAA_PME
- printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
+ printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
#endif
- puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
+ puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
#ifdef CONFIG_FSL_CORENET
/* Display the RCW, so that no one gets confused as to what RCW
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2d65157c7fd03d5e5c93dedf0a1aa267c6374d58..6036333eaa72fba3ac3e3378d42abb06dce12d6e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -167,7 +167,8 @@ static void enable_cpc(void)
}
- printf("Corenet Platform Cache: %d KB enabled\n", size);
+ puts("Corenet Platform Cache: ");
+ print_size(size * 1024, " enabled\n");
}
static void invalidate_cpc(void)
@@ -356,7 +357,9 @@ int cpu_init_r(void)
extern int spin_table_compat;
const char *spin;
#endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
+ ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
@@ -457,28 +460,28 @@ int cpu_init_r(void)
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8555) {
- puts("128 KB ");
- /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
+ puts("128 KiB ");
+ /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
cache_ctl = 0xc4000000;
} else {
- puts("256 KB ");
+ puts("256 KiB ");
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
}
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8555) {
- puts("256 KB ");
- /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
+ puts("256 KiB ");
+ /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
cache_ctl = 0xc8000000;
} else {
- puts ("512 KB ");
+ puts("512 KiB ");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
}
break;
case 0x3:
- puts("1024 KB ");
+ puts("1024 KiB ");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
break;
@@ -526,13 +529,14 @@ int cpu_init_r(void)
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
;
- printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
+ print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
}
skip_l2:
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
if (l2cache->l2csr0 & L2CSR0_L2E)
- printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+ print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
+ " enabled\n");
enable_cluster_l2();
#else
@@ -546,6 +550,12 @@ skip_l2:
fsl_serdes_init();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
+#define MCFGR_AXIPIPE 0x000000f0
+ if (IS_SVR_REV(svr, 1, 0))
+ clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
int i;
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 84bb8fab8fe7f9ce7fe651c04a79092fdeb61612..533d47ab438a86889ec0b0dbc0ccc54f2f1bf00c 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -403,22 +403,22 @@ static void ft_fixup_dpaa_clks(void *blob)
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_DPAA_FMAN
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
- sysinfo.freqFMan[0]);
+ sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
- sysinfo.freqFMan[1]);
+ sysinfo.freq_fman[1]);
#endif
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
do_fixup_by_compat_u32(blob, "fsl,qman",
- "clock-frequency", sysinfo.freqQMAN, 1);
+ "clock-frequency", sysinfo.freq_qman, 1);
#endif
#ifdef CONFIG_SYS_DPAA_PME
do_fixup_by_compat_u32(blob, "fsl,pme",
- "clock-frequency", sysinfo.freqPME, 1);
+ "clock-frequency", sysinfo.freq_pme, 1);
#endif
}
#else
@@ -476,7 +476,7 @@ void fdt_fixup_fman_firmware(void *blob)
if (!p)
return;
- fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0);
+ fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16);
if (!fmanfw)
return;
@@ -616,7 +616,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
- val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
+ val = cpu_to_fdt32(sysinfo.freq_processor[*reg]);
fdt_setprop(blob, off, "clock-frequency", &val, 4);
off = fdt_node_offset_by_prop_value(blob, off, "device_type",
"cpu", 4);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f093960fe7e7139cfec9e164f8ff9a5b97a25aaa..07690f97b16a9ca9e2095233b65f60c4c23ff364 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------- */
-void get_sys_info (sys_info_t * sysInfo)
+void get_sys_info(sys_info_t *sys_info)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
@@ -46,7 +46,7 @@ void get_sys_info (sys_info_t * sysInfo)
[14] = 3, /* CC4 PPL / 4 */
};
- const u8 core_cplx_PLL_div[16] = {
+ const u8 core_cplx_pll_div[16] = {
[ 0] = 1, /* CC1 PPL / 1 */
[ 1] = 2, /* CC1 PPL / 2 */
[ 2] = 4, /* CC1 PPL / 4 */
@@ -60,26 +60,26 @@ void get_sys_info (sys_info_t * sysInfo)
[13] = 2, /* CC4 PPL / 2 */
[14] = 4, /* CC4 PPL / 4 */
};
- uint i, freqCC_PLL[6], rcw_tmp;
+ uint i, freq_cc_pll[6], rcw_tmp;
uint ratio[6];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
- sysInfo->freqSystemBus = sysclk;
+ sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
- sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else
- sysInfo->freqDDRBus = sysclk;
+ sys_info->freq_ddrbus = sysclk;
#endif
- sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
if (mem_pll_rat > 2)
- sysInfo->freqDDRBus *= mem_pll_rat;
+ sys_info->freq_ddrbus *= mem_pll_rat;
else
- sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
+ sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
@@ -89,9 +89,9 @@ void get_sys_info (sys_info_t * sysInfo)
ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
for (i = 0; i < 6; i++) {
if (ratio[i] > 4)
- freqCC_PLL[i] = sysclk * ratio[i];
+ freq_cc_pll[i] = sysclk * ratio[i];
else
- freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+ freq_cc_pll[i] = sys_info->freq_systembus * ratio[i];
}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
@@ -110,8 +110,8 @@ void get_sys_info (sys_info_t * sysInfo)
printf("Unsupported architecture configuration"
" in function %s\n", __func__);
cplx_pll += (cluster / 2) * 3;
- sysInfo->freqProcessor[cpu] =
- freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+ sys_info->freq_processor[cpu] =
+ freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
#ifdef CONFIG_PPC_B4860
#define FM1_CLK_SEL 0xe0000000
@@ -127,63 +127,63 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_SYS_DPAA_PME
switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
case 1:
- sysInfo->freqPME = freqCC_PLL[0];
+ sys_info->freq_pme = freq_cc_pll[0];
break;
case 2:
- sysInfo->freqPME = freqCC_PLL[0] / 2;
+ sys_info->freq_pme = freq_cc_pll[0] / 2;
break;
case 3:
- sysInfo->freqPME = freqCC_PLL[0] / 3;
+ sys_info->freq_pme = freq_cc_pll[0] / 3;
break;
case 4:
- sysInfo->freqPME = freqCC_PLL[0] / 4;
+ sys_info->freq_pme = freq_cc_pll[0] / 4;
break;
case 6:
- sysInfo->freqPME = freqCC_PLL[1] / 2;
+ sys_info->freq_pme = freq_cc_pll[1] / 2;
break;
case 7:
- sysInfo->freqPME = freqCC_PLL[1] / 3;
+ sys_info->freq_pme = freq_cc_pll[1] / 3;
break;
default:
printf("Error: Unknown PME clock select!\n");
case 0:
- sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ sys_info->freq_pme = sys_info->freq_systembus / 2;
break;
}
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+ sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
case 1:
- sysInfo->freqFMan[0] = freqCC_PLL[3];
+ sys_info->freq_fman[0] = freq_cc_pll[3];
break;
case 2:
- sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
+ sys_info->freq_fman[0] = freq_cc_pll[3] / 2;
break;
case 3:
- sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
+ sys_info->freq_fman[0] = freq_cc_pll[3] / 3;
break;
case 4:
- sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
+ sys_info->freq_fman[0] = freq_cc_pll[3] / 4;
break;
case 5:
- sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+ sys_info->freq_fman[0] = sys_info->freq_systembus;
break;
case 6:
- sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
+ sys_info->freq_fman[0] = freq_cc_pll[4] / 2;
break;
case 7:
- sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
+ sys_info->freq_fman[0] = freq_cc_pll[4] / 3;
break;
default:
printf("Error: Unknown FMan1 clock select!\n");
case 0:
- sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
break;
}
#if (CONFIG_SYS_NUM_FMAN) == 2
@@ -192,27 +192,27 @@ void get_sys_info (sys_info_t * sysInfo)
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
case 1:
- sysInfo->freqFMan[1] = freqCC_PLL[4];
+ sys_info->freq_fman[1] = freq_cc_pll[4];
break;
case 2:
- sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
+ sys_info->freq_fman[1] = freq_cc_pll[4] / 2;
break;
case 3:
- sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
+ sys_info->freq_fman[1] = freq_cc_pll[4] / 3;
break;
case 4:
- sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
+ sys_info->freq_fman[1] = freq_cc_pll[4] / 4;
break;
case 6:
- sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
+ sys_info->freq_fman[1] = freq_cc_pll[3] / 2;
break;
case 7:
- sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
+ sys_info->freq_fman[1] = freq_cc_pll[3] / 3;
break;
default:
printf("Error: Unknown FMan2 clock select!\n");
case 0:
- sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
break;
}
#endif /* CONFIG_SYS_NUM_FMAN == 2 */
@@ -225,8 +225,8 @@ void get_sys_info (sys_info_t * sysInfo)
& 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
- sysInfo->freqProcessor[cpu] =
- freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+ sys_info->freq_processor[cpu] =
+ freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
@@ -246,43 +246,43 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_SYS_DPAA_PME
if (rcw_tmp & PME_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
- sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
+ sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4;
else
- sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
+ sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2;
} else {
- sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ sys_info->freq_pme = sys_info->freq_systembus / 2;
}
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
if (rcw_tmp & FM1_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
- sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
+ sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4;
else
- sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
+ sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2;
} else {
- sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
}
#if (CONFIG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
- sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
+ sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4;
else
- sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
+ sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2;
} else {
- sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
}
#endif
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+ sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else /* CONFIG_FSL_CORENET */
- uint plat_ratio, e500_ratio, half_freqSystemBus;
+ uint plat_ratio, e500_ratio, half_freq_systembus;
int i;
#ifdef CONFIG_QE
__maybe_unused u32 qe_ratio;
@@ -290,40 +290,40 @@ void get_sys_info (sys_info_t * sysInfo)
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
- sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
- half_freqSystemBus = sysInfo->freqSystemBus/2;
+ half_freq_systembus = sys_info->freq_systembus/2;
for (i = 0; i < cpu_numcores(); i++) {
e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
- sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
+ sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
}
- /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
- sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+ /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
+ sys_info->freq_ddrbus = sys_info->freq_systembus;
#ifdef CONFIG_DDR_CLK_FREQ
{
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
- sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
- sysInfo->freqQE = sysInfo->freqSystemBus;
+ sys_info->freq_qe = sys_info->freq_systembus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
- sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
- sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+ sys_info->freq_fman[0] = sys_info->freq_systembus;
#endif
#endif /* CONFIG_FSL_CORENET */
@@ -350,10 +350,10 @@ void get_sys_info (sys_info_t * sysInfo)
*/
lcrr_div *= 2;
#endif
- sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
+ sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
} else {
/* In case anyone cares what the unknown value is */
- sysInfo->freqLocalBus = lcrr_div;
+ sys_info->freq_localbus = lcrr_div;
}
#endif
@@ -361,7 +361,7 @@ void get_sys_info (sys_info_t * sysInfo)
ccr = in_be32(&ifc_regs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
- sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
+ sys_info->freq_localbus = sys_info->freq_systembus / ccr;
#endif
}
@@ -382,13 +382,13 @@ int get_clocks (void)
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
- gd->cpu_clk = sys_info.freqProcessor[0];
- gd->bus_clk = sys_info.freqSystemBus;
- gd->mem_clk = sys_info.freqDDRBus;
- gd->arch.lbc_clk = sys_info.freqLocalBus;
+ gd->cpu_clk = sys_info.freq_processor[0];
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->mem_clk = sys_info.freq_ddrbus;
+ gd->arch.lbc_clk = sys_info.freq_localbus;
#ifdef CONFIG_QE
- gd->arch.qe_clk = sys_info.freqQE;
+ gd->arch.qe_clk = sys_info.freq_qe;
gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
/*
@@ -400,7 +400,7 @@ int get_clocks (void)
*/
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
- gd->arch.i2c1_clk = sys_info.freqSystemBus;
+ gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
@@ -410,12 +410,12 @@ int get_clocks (void)
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
+ gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
else
- gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
- gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#endif
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
@@ -429,7 +429,7 @@ int get_clocks (void)
#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
- gd->arch.vco_out = 2*sys_info.freqSystemBus;
+ gd->arch.vco_out = 2*sys_info.freq_systembus;
gd->arch.cpm_clk = gd->arch.vco_out / 2;
gd->arch.scc_clk = gd->arch.vco_out / 4;
gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index ed88602c3158301b73c2a2cc9f910bea1565fcc8..ff55e3c357c3371b9f078d3da40550b3710a7cd4 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -106,25 +106,25 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM1_A, NONE}},
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM2_MAC10, XFI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index da3c345d6f787bf641fd38c91055f98f604efdc0..8748ecd1440d1ea53811d4a4e937c39428f9fc3c 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -39,7 +39,8 @@ void init_tlbs(void)
return ;
}
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && \
+ (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 08188d75e5f12cf5a64f4f40aeae4066186311c6..85ec74ba94adbfeedef1e339d10f06a3ded6d034 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -44,6 +44,11 @@ SECTIONS
}
_edata = .;
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
. = ALIGN(8);
__init_begin = .;
__init_end = .;
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index d6b28dd077c5a2740905479fd5f72c546af11cc0..30518544dd65827e723d054785b1edcc8a3c0017 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -72,21 +72,21 @@ checkcpu(void)
get_sys_info(&sysinfo);
puts("Clock Configuration:\n");
- printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
- printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
+ printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
+ printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
- strmhz(buf1, sysinfo.freqSystemBus / 2),
- strmhz(buf2, sysinfo.freqSystemBus));
+ strmhz(buf1, sysinfo.freq_systembus / 2),
+ strmhz(buf2, sysinfo.freq_systembus));
- if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
- printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+ if (sysinfo.freq_localbus > LCRR_CLKDIV) {
+ printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
- sysinfo.freqLocalBus);
+ sysinfo.freq_localbus);
}
- puts("L1: D-cache 32 KB enabled\n");
- puts(" I-cache 32 KB enabled\n");
+ puts("L1: D-cache 32 KiB enabled\n");
+ puts(" I-cache 32 KiB enabled\n");
puts("L2: ");
if (get_l2cr() & 0x80000000) {
@@ -95,7 +95,7 @@ checkcpu(void)
#elif defined(CONFIG_MPC8641)
puts("512");
#endif
- puts(" KB enabled\n");
+ puts(" KiB enabled\n");
} else {
puts("Disabled\n");
}
@@ -131,7 +131,7 @@ get_tbclk(void)
sys_info_t sys_info;
get_sys_info(&sys_info);
- return (sys_info.freqSystemBus + 3L) / 4L;
+ return (sys_info.freq_systembus + 3L) / 4L;
}
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index ea366ab9e4c18dd7163ad1e2a681a434e67c8823..854d02b5c49211ea526329202efd124978bb9bff 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
extern unsigned long get_board_sys_clk(unsigned long dummy);
-void get_sys_info(sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sys_info)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -31,7 +31,7 @@ void get_sys_info(sys_info_t *sysInfo)
switch (plat_ratio) {
case 0x0:
- sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
break;
case 0x02:
case 0x03:
@@ -43,10 +43,10 @@ void get_sys_info(sys_info_t *sysInfo)
case 0x0a:
case 0x0c:
case 0x10:
- sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
break;
default:
- sysInfo->freqSystemBus = 0;
+ sys_info->freq_systembus = 0;
break;
}
@@ -55,25 +55,26 @@ void get_sys_info(sys_info_t *sysInfo)
switch (e600_ratio) {
case 0x10:
- sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
+ sys_info->freq_processor = 2 * sys_info->freq_systembus;
break;
case 0x19:
- sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2;
+ sys_info->freq_processor = 5 * sys_info->freq_systembus / 2;
break;
case 0x20:
- sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
+ sys_info->freq_processor = 3 * sys_info->freq_systembus;
break;
case 0x39:
- sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2;
+ sys_info->freq_processor = 7 * sys_info->freq_systembus / 2;
break;
case 0x28:
- sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
+ sys_info->freq_processor = 4 * sys_info->freq_systembus;
break;
case 0x1d:
- sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2;
+ sys_info->freq_processor = 9 * sys_info->freq_systembus / 2;
break;
default:
- sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
+ sys_info->freq_processor = e600_ratio +
+ sys_info->freq_systembus;
break;
}
@@ -84,10 +85,11 @@ void get_sys_info(sys_info_t *sysInfo)
lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
- sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
+ sys_info->freq_localbus = sys_info->freq_systembus
+ / (lcrr_div * 2);
} else {
/* In case anyone cares what the unknown value is */
- sysInfo->freqLocalBus = lcrr_div;
+ sys_info->freq_localbus = lcrr_div;
}
}
@@ -102,9 +104,9 @@ int get_clocks(void)
sys_info_t sys_info;
get_sys_info(&sys_info);
- gd->cpu_clk = sys_info.freqProcessor;
- gd->bus_clk = sys_info.freqSystemBus;
- gd->arch.lbc_clk = sys_info.freqLocalBus;
+ gd->cpu_clk = sys_info.freq_processor;
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->arch.lbc_clk = sys_info.freq_localbus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
@@ -114,9 +116,9 @@ int get_clocks(void)
* AN2919.
*/
#ifdef CONFIG_MPC8610
- gd->arch.i2c1_clk = sys_info.freqSystemBus;
+ gd->arch.i2c1_clk = sys_info.freq_systembus;
#else
- gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#endif
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
@@ -138,7 +140,7 @@ ulong get_bus_freq(ulong dummy)
sys_info_t sys_info;
get_sys_info(&sys_info);
- val = sys_info.freqSystemBus;
+ val = sys_info.freq_systembus;
return val;
}
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 1550045e6c79d3fcd1f1d77e52fa1b344eba8611..5c96b5fe16e7e6bd2d4e0d9b9190c5c31a13fd7a 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -136,10 +136,8 @@ static int check_CPU (long clock, uint pvr, uint immr)
#else
printf (" at %s MHz: ", strmhz (buf, clock));
#endif
- printf ("%u kB I-Cache %u kB D-Cache",
- checkicache () >> 10,
- checkdcache () >> 10
- );
+ print_size(checkicache(), " I-Cache ");
+ print_size(checkdcache(), " D-Cache");
/* do we have a FEC (860T/P or 852/859/866/885)? */
@@ -204,10 +202,10 @@ static int check_CPU (long clock, uint pvr, uint immr)
printf ("unknown MPC857 (0x%08x)", k);
#endif
- printf (" at %s MHz:", strmhz (buf, clock));
+ printf(" at %s MHz: ", strmhz(buf, clock));
- printf (" %u kB I-Cache", checkicache () >> 10);
- printf (" %u kB D-Cache", checkdcache () >> 10);
+ print_size(checkicache(), " I-Cache ");
+ print_size(checkdcache(), " D-Cache");
/* lets check and see if we're running on a 862T (or P?) */
@@ -265,10 +263,10 @@ static int check_CPU (long clock, uint pvr, uint immr)
if (suf)
printf ("PPC823ZTnn%s", suf);
- printf (" at %s MHz:", strmhz (buf, clock));
+ printf(" at %s MHz: ", strmhz(buf, clock));
- printf (" %u kB I-Cache", checkicache () >> 10);
- printf (" %u kB D-Cache", checkdcache () >> 10);
+ print_size(checkicache(), " I-Cache ");
+ print_size(checkdcache(), " D-Cache");
/* lets check and see if we're running on a 860T (or P?) */
@@ -321,10 +319,10 @@ static int check_CPU (long clock, uint pvr, uint immr)
default:
printf ("unknown MPC850 (0x%08x)", k);
}
- printf (" at %s MHz:", strmhz (buf, clock));
+ printf(" at %s MHz: ", strmhz(buf, clock));
- printf (" %u kB I-Cache", checkicache () >> 10);
- printf (" %u kB D-Cache", checkdcache () >> 10);
+ print_size(checkicache(), " I-Cache ");
+ print_size(checkdcache(), " D-Cache");
/* lets check and see if we're running on a 850T (or P?) */
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 02a0467896c7e62df1ac9a9d42fdbd490a7b3195..fc351585bef8c989fe717205260fdea4febd24bd 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -1176,7 +1176,7 @@ static void *video_logo (void)
#ifndef CONFIG_FADS /* all normal boards */
/* leave one blank line */
- sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash",
+ sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash",
strmhz(temp, gd->cpu_clk),
gd->ram_size >> 20,
gd->bd->bi_flashsize >> 20 );
@@ -1187,7 +1187,7 @@ static void *video_logo (void)
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
info);
- sprintf (info, "2MB FLASH - 8MB DRAM - 4MB SRAM");
+ sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index e958e138dda6c613f747a2b806dc1d58476a83a8..56128a7b962ca062c0eab7e878dde4c4bada8041 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -218,12 +218,16 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
if (dimm_params[i].n_ranks) {
if (dimm_params[i].registered_dimm) {
temp1 = 1;
+#ifndef CONFIG_SPL_BUILD
printf("Detected RDIMM %s\n",
dimm_params[i].mpart);
+#endif
} else {
temp2 = 1;
+#ifndef CONFIG_SPL_BUILD
printf("Detected UDIMM %s\n",
dimm_params[i].mpart);
+#endif
}
}
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 9f4f25343b4fa5d0fdd0883946eec13bef5d326f..842bf1989e3edcca59e879f5e03da6f3b4a96162 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -683,7 +683,8 @@ phys_size_t fsl_ddr_sdram(void)
#if !defined(CONFIG_PHYS_64BIT)
/* Check for 4G or more. Bad. */
if (total_memory >= (1ull << 32)) {
- printf("Detected %lld MB of memory\n", total_memory >> 20);
+ puts("Detected ");
+ print_size(total_memory, " of memory\n");
printf(" This U-Boot only supports < 4G of DDR\n");
printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
printf(" "); /* re-align to match init_func_ram print */
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 89a561e0aca3b5ed87ca745799f649546d3d976e..a401083107794cc3dd218cf88e7edc58c7858063 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -76,7 +76,8 @@ void disable_law(u8 idx)
return;
}
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && \
+ (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
@@ -106,7 +107,8 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
return idx;
}
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && \
+ (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 5cebafdbae6a0550f68daee093bfcf6189dbfef5..d1fc7f3fc2ae789c7e1181b8cb68161c9c09e864 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -631,12 +631,12 @@ int checkcpu (void)
#endif
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
- printf (" 16 kB I-Cache 16 kB D-Cache");
+ printf(" 16 KiB I-Cache 16 KiB D-Cache");
#elif defined(CONFIG_440)
- printf (" 32 kB I-Cache 32 kB D-Cache");
+ printf(" 32 KiB I-Cache 32 KiB D-Cache");
#else
- printf (" 16 kB I-Cache %d kB D-Cache",
- ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
+ printf(" 16 KiB I-Cache %d KiB D-Cache",
+ ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_405) */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index cf1bb027970cfd173e31ab97552616a761c2d1fc..15e44de41e66f997ed41f6520f882674f9238469 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -133,6 +133,7 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 6e64745b0fa374c5bc88012eceb4f191fc195a8a..db0cf28fffbb882d68115bc048f450558c42f766 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -13,10 +13,10 @@
static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
@@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
{-1, -1}, {-1, -1} };
#ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
@@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
-static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
@@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
{-1, -1}, {-1, -1} };
#ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 457d1adbdc1c902e98d1aa8b90ff5babec654a4d..f9550c48ceba642e6db2707615d962ffad80158c 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -45,9 +45,7 @@ COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
-ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
-endif
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c
index 8a3dc33b66c748ccc85665c087368be2362ab452..97a25e838ed414080c7140baba7e6e4ebcf63b0d 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
}
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
{
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
index 4003fcdb23d82f2e112c4641fcfe44ddbed2cd7a..2a491877792fdeef574a66929da6f692f9cccb7c 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
#include <errno.h>
int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 7a84cd295a2d5ea3c6bf69193c02aba1e8508ffd..2fb40374283cdb07bc132cadc78a45bd49e865bb 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -68,7 +68,7 @@ local_bus_init(void)
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 3d2dabd1169a52087d644796a48ddb26288c2514..1e21a664c1f424af2e15a7c788a3063271ed53f8 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -250,7 +250,7 @@ local_bus_init(void)
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index d4e7abebd43449dc68a1aa6c690e94acc0d9c439..ee9269504cb3c558a63479e0b671138865e61385 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -248,7 +248,7 @@ local_bus_init(void)
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index a45a5583c9362ad3739bdd771f337ee458417a11..162636ef8c0bbdeb98b6183c6b62e6f9cd00727b 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -273,7 +273,7 @@ local_bus_init(void)
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index 73289f3656d93702e2bf2389813f1bc4c3f92bcd..d0e712eb303112fadc49e5182b28867d336ab244 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -26,7 +26,7 @@ void sdram_init(void)
ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+ ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
/* mask off E bit */
u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index cfc05f71243c1979d986f7355d4f4d46542e1409..3bc4f4325f0593eeb07f3fa6a017f91794f55629 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -21,6 +21,9 @@ ifdef MINIMAL
COBJS-y += spl_minimal.o tlb.o law.o
else
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..b9dbf81b3f89b0024a0c1c2bca0ee704bc456070
--- /dev/null
+++ b/board/freescale/p1022ds/spl.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/ngpixis.h"
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+ 66666000, 7499900, 83332500, 8999900,
+ 99999000, 11111000, 12499800, 13333200
+};
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ int px_spd;
+ u32 plat_ratio, sys_clk, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ /* Enable the SPI */
+ clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+#endif
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+ /* initialize selected port with appropriate baud rate */
+ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+ sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ bus_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+ i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index d150d95a2f0bc9bce9ef17399f5b5b720a15d8d7..8b343968437be445424cc94d06d71f7c20e9f115 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -12,51 +12,6 @@
#include <asm/fsl_ddr_sdram.h>
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
- __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
- __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
- &ddr->sdram_cfg);
-
- in_be32(&ddr->sdram_cfg);
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
- in_be32(&ddr->sdram_cfg);
-
- set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
const static u32 sysclk_tbl[] = {
66666000, 7499900, 83332500, 8999900,
99999000, 11111000, 12499800, 13333200
@@ -68,6 +23,10 @@ void board_init_f(ulong bootflag)
u32 plat_ratio, sys_clk, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
/* for FPGA */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
@@ -83,9 +42,6 @@ void board_init_f(ulong bootflag)
puts("\nNAND boot... ");
- /* Initialize the DDR3 */
- sdram_init();
-
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
@@ -96,6 +52,7 @@ void board_init_f(ulong bootflag)
void board_init_r(gd_t *gd, ulong dest_addr)
{
+ puts("\nSecond program loader running in sram...");
nand_boot();
}
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index 2eef6adbfa86717107571d319ab1a58705f1cb82..e7ae2e25b224acf62009cc39760c2b4e36ea5f30 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -71,25 +71,32 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* **** - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1),
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_1G, 1),
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16K, 1),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16K, 1),
#endif
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 5c51845ddfc0e95e92b9197aff9fa7a12701e25d..c0b72e035e924a9e295165b6d92c9e4a48ee5fa4 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -247,7 +247,7 @@ phys_size_t fixed_sdram(void)
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freqDDRBus));
+ strmhz(buf, sysinfo.freq_ddrbus));
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index 697c0dd370251f268d36bacf61c9f4a385d4a79a..67f69d79bd6fcbabaf7523d9ef56e0d3ed984882 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -53,7 +53,7 @@ phys_size_t fixed_sdram(void)
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freqDDRBus));
+ strmhz(buf, sysinfo.freq_ddrbus));
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index c771e17952c888b01c6963c90fdc56f8737063b5..b5f488bcba46c6d6de8b70db79cd3afd354ba5b9 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -172,7 +172,10 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ int interface = fm_info_get_enet_if(port);
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
if (qsgmiiphy_fix[port])
@@ -272,6 +275,7 @@ void fdt_fixup_board_enet(void *fdt)
for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
switch (mdio_mux[i]) {
case EMI1_SLOT1:
fdt_status_okay_by_alias(fdt, "emi1_slot1");
@@ -393,7 +397,7 @@ static void initialize_qsgmiiphy_fix(void)
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot;
+ int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -470,9 +474,9 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][3]);
- fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
+ fm_info_set_phy_address(FM1_DTSEC10,
+ slot_qsgmii_phyaddr[1][3]);
}
break;
case 40:
@@ -482,9 +486,9 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][3]);
- fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][2]);
+ fm_info_set_phy_address(FM1_DTSEC9,
+ slot_qsgmii_phyaddr[1][3]);
}
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
@@ -498,15 +502,31 @@ int board_eth_init(bd_t *bis)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
- switch (fm_info_get_enet_if(i)) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_QSGMII) {
+ if (idx <= 3)
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_B);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
+ idx + 1, slot);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ }
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
@@ -600,8 +620,8 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
break;
case 40:
case 46:
@@ -641,15 +661,31 @@ int board_eth_init(bd_t *bis)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
idx = i - FM2_DTSEC1;
- switch (fm_info_get_enet_if(i)) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(FSL_SRDS_2,
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_QSGMII) {
+ if (idx <= 3)
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ QSGMII_FM2_A);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ QSGMII_FM2_B);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
+ idx + 1, slot);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_2,
SGMII_FM2_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- debug("FM2@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ }
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 7ee0f547866913edb03d56df021d308376a69525..0c1a4fbd9ff7b4f6a44656f740290a8e15f23f15 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -26,16 +26,16 @@
DECLARE_GLOBAL_DATA_PTR;
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
{10, 11}, {11, 10}, {12, 2}, {13, 3} };
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
{8, 9}, {9, 8}, {14, 1}, {15, 0} };
int checkboard(void)
@@ -353,25 +353,60 @@ int config_frontside_crossbar_vsc3316(void)
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- if (srds_prtcl_s1) {
+ switch (srds_prtcl_s1) {
+ case 38:
+ /* swap first lane and third lane on slot1 */
+ vsc3316_fsm1_tx[0][1] = 14;
+ vsc3316_fsm1_tx[6][1] = 0;
+ vsc3316_fsm1_rx[1][1] = 2;
+ vsc3316_fsm1_rx[6][1] = 13;
+ case 40:
+ case 46:
+ case 48:
+ /* swap first lane and third lane on slot2 */
+ vsc3316_fsm1_tx[2][1] = 8;
+ vsc3316_fsm1_tx[4][1] = 6;
+ vsc3316_fsm1_rx[2][1] = 10;
+ vsc3316_fsm1_rx[5][1] = 5;
+ default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
if (ret)
return ret;
+ break;
}
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- if (srds_prtcl_s2) {
+ switch (srds_prtcl_s2) {
+ case 38:
+ /* swap first lane and third lane on slot3 */
+ vsc3316_fsm2_tx[2][1] = 11;
+ vsc3316_fsm2_tx[5][1] = 4;
+ vsc3316_fsm2_rx[2][1] = 9;
+ vsc3316_fsm2_rx[4][1] = 7;
+ case 40:
+ case 46:
+ case 48:
+ case 50:
+ case 52:
+ case 54:
+ /* swap first lane and third lane on slot4 */
+ vsc3316_fsm2_tx[6][1] = 3;
+ vsc3316_fsm2_tx[1][1] = 12;
+ vsc3316_fsm2_rx[0][1] = 1;
+ vsc3316_fsm2_rx[6][1] = 15;
+ default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
if (ret)
return ret;
+ break;
}
return 0;
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index dee8710316023523d7b8055fc492d1df66f23ad7..837851838d6b93dae8f882f490ce17bff8d758ed 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -65,8 +65,8 @@ local_bus_init(void)
get_sys_info(&sysinfo);
- lbc_mhz = sysinfo.freqLocalBus / 1000000;
- clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus;
+ lbc_mhz = sysinfo.freq_localbus / 1000000;
+ clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 97fd0e4bd10ca7d68919251b4655906242312acf..2caefbbe5844a217b4380160b00044c60b609826 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -143,7 +143,7 @@ void local_bus_init (void)
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+ lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
if (lbc_mhz >= 66)
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
index 0daa189103da337859898d331ed73b0e2a4f6103..c128fcb53dbb6734af04c713f1ea6f1632f69544 100644
--- a/board/xes/xpedite537x/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
@@ -210,7 +210,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
unsigned int datarate;
get_sys_info(&sysinfo);
- datarate = sysinfo.freqDDRBus / 1000 / 1000;
+ datarate = sysinfo.freq_ddrbus / 1000 / 1000;
for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
if ((bopts[i].datarate_mhz_low <= datarate) &&
diff --git a/common/env_common.c b/common/env_common.c
index f387f9ab91f6897acb24b1e55c204279f6e26657..1ac337730c3ec0d1f467e951497cfa1c5be16c6b 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -140,7 +140,6 @@ int set_default_vars(int nvars, char * const vars[])
H_NOCLEAR | H_INTERACTIVE, nvars, vars);
}
-#ifndef CONFIG_SPL_BUILD
/*
* Check if CRC is valid and (if yes) import the environment.
* Note that "buf" may or may not be aligned.
@@ -172,7 +171,6 @@ int env_import(const char *buf, int check)
return 0;
}
-#endif
void env_relocate(void)
{
diff --git a/config.mk b/config.mk
index 54e99f4da31012a11b7e82e2589db214d09f989a..b3ecaa7f80abcc62beb81da2b44be1dc585c3a88 100644
--- a/config.mk
+++ b/config.mk
@@ -13,6 +13,12 @@ SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
export SHELL
+ifeq ($(CONFIG_TPL_BUILD),y)
+SPL_BIN := u-boot-tpl
+else
+SPL_BIN := u-boot-spl
+endif
+
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
@@ -22,7 +28,11 @@ endif
ifneq ($(OBJTREE),$(SRCTREE))
# Create object files for SPL in a separate directory
ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_TPL_BUILD),y)
+obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
+else
obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
+endif
else
obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/)
endif
@@ -32,8 +42,12 @@ $(shell mkdir -p $(obj))
else
# Create object files for SPL in a separate directory
ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_TPL_BUILD),y)
+obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
+else
obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
+endif
$(shell mkdir -p $(obj))
else
obj :=
@@ -145,6 +159,10 @@ CHECK = sparse
#########################################################################
# Load generated board configuration
+ifeq ($(CONFIG_TPL_BUILD),y)
+# Include TPL autoconf
+sinclude $(OBJTREE)/include/tpl-autoconf.mk
+else
ifeq ($(CONFIG_SPL_BUILD),y)
# Include SPL autoconf
sinclude $(OBJTREE)/include/spl-autoconf.mk
@@ -152,6 +170,7 @@ else
# Include normal autoconf
sinclude $(OBJTREE)/include/autoconf.mk
endif
+endif
sinclude $(OBJTREE)/include/config.mk
# Some architecture config.mk files need to know what CPUDIR is set to,
@@ -221,12 +240,19 @@ ifneq ($(CONFIG_SPL_PAD_TO),)
CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO)
endif
+ifneq ($(CONFIG_TPL_PAD_TO),)
+CPPFLAGS += -DCONFIG_TPL_PAD_TO=$(CONFIG_TPL_PAD_TO)
+endif
+
ifneq ($(CONFIG_UBOOT_PAD_TO),)
CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO)
endif
ifeq ($(CONFIG_SPL_BUILD),y)
CPPFLAGS += -DCONFIG_SPL_BUILD
+ifeq ($(CONFIG_TPL_BUILD),y)
+CPPFLAGS += -DCONFIG_TPL_BUILD
+endif
endif
# Does this architecture support generic board init?
@@ -298,9 +324,9 @@ ifneq ($(CONFIG_SYS_TEXT_BASE),)
LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
endif
-LDFLAGS_u-boot-spl += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL)
+LDFLAGS_$(SPL_BIN) += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL)
ifneq ($(CONFIG_SPL_TEXT_BASE),)
-LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE)
+LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
endif
# Linus' kernel sanity checking tool
diff --git a/doc/README.TPL b/doc/README.TPL
new file mode 100644
index 0000000000000000000000000000000000000000..1df03b958ea6ad454c66e78475b2599f06b80738
--- /dev/null
+++ b/doc/README.TPL
@@ -0,0 +1,45 @@
+Generic TPL framework
+=====================
+
+Overview
+--------
+
+TPL---Third Program Loader.
+
+Due to the SPL on some boards(powerpc mpc85xx) has a size limit and cannot
+be compatible with all the external device(e.g. DDR). So add a tertiary
+program loader (TPL) to enable a loader stub loaded by the code from the
+SPL. It loads the final uboot image into DDR, then jump to it to begin
+execution. Now, only the powerpc mpc85xx has this requirement and will
+implemente it.
+
+Keep consistent with SPL, with this framework almost all source files for a
+board can be reused. No code duplication or symlinking is necessary anymore.
+
+How it works
+------------
+
+There has been a directory TOPDIR/spl which contains only a Makefile. The
+Makefile is shared by SPL and TPL.
+
+The object files are built separately for SPL/TPL and placed in the
+directory spl/tpl. The final binaries which are generated are
+u-boot-{spl|tpl}, u-boot-{spl|tpl}.bin and u-boot-{spl|tpl}.map.
+
+During the TPL build a variable named CONFIG_TPL_BUILD is exported in the
+make environment and also appended to CPPFLAGS with -DCONFIG_TPL_BUILD.
+
+The SPL options are shared by SPL and TPL, the board config file should
+determine which SPL options to choose based on whether CONFIG_TPL_BUILD
+is set. Source files can be compiled for TPL with options choosed in the
+board config file.
+
+For example:
+
+spl/Makefile:
+LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
+
+CONFIG_SPL_LIBCOMMON_SUPPORT is defined in board config file:
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#endif
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
new file mode 100644
index 0000000000000000000000000000000000000000..d5043ccb66cff97d964beb9366684d6953e4d1ce
--- /dev/null
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -0,0 +1,81 @@
+----------------------------------------
+Booting from On-Chip ROM (eSDHC or eSPI)
+----------------------------------------
+
+boot_format is a tool to write SD bootable images to a filesystem and build
+SD/SPI images to a binary file for writing later.
+
+When booting from an SD card/MMC, boot_format puts the configuration file and
+the RAM-based U-Boot image on the card.
+When booting from an EEPROM, boot_format generates a binary image that is used
+to boot from this EEPROM.
+
+Where to get boot_format:
+========================
+
+you can browse it online at:
+http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/
+
+Building
+========
+
+Run the following to build this project
+
+ $ make
+
+Execution
+=========
+
+boot_format runs under a regular Linux machine and requires a super user mode
+to run. Execute boot_format as follows.
+
+For building SD images by writing directly to a file system on SD media:
+
+ $ boot_format $config u-boot.bin -sd $device
+
+Where $config is the included config.dat file for your platform and $device
+is the target block device for the SD media on your computer.
+
+For build binary images directly a local file:
+
+ $ boot_format $config u-boot.bin -spi $file
+
+Where $file is the target file. Also keep in mind the u-boot.bin file needs
+to be the u-boot built for your particular platform and target media.
+
+Example: To generate a u-boot.bin for a P1022DS booting from SD, run the
+following in the u-boot repository:
+
+ $ make P1022DS_SDCARD
+
+Configuration Files
+===================
+
+Below are the configuration files to be used with a particular platform. Keep
+in mind that some of these config files are tied to the platforms DDR speed.
+Please see the SoC reference manual for more documentation.
+
+P1022DS config_sram_p1022ds.dat
+P2020DS config_sram_p2020ds.dat
+P2010DS config_sram_p2020ds.dat
+P1020RDB config_ddr2_1g_p1020rdb_533M.dat
+P1020RDB config_ddr2_1g_p1020rdb_667M.dat
+P2020RDB config_ddr2_1g_p2020rdb_800M.dat
+P2020RDB config_ddr2_1g_p2020rdb_667M.dat
+P2020RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat
+P2010RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat
+P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
+P1014RDB config_ddr3_1gb_p1014rdb_800M.dat
+P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1012RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1022DS config_ddr3_2gb_p1022ds.dat
+P1013DS config_ddr3_2gb_p1022ds.dat
+P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1013RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1025RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1016RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1020MBG config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+MPC8536DS config_ddr2_512m_mpc8536ds_667M.dat
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 49e5cb9c2a494de55d097ba85d880348dd5a8bb8..bedf833f70dfac17344af3195cfb33582c96ab34 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -32,6 +32,9 @@ COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
COBJS-$(CONFIG_DWMMC) += dw_mmc.o
COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
COBJS-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
+endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..65c52a22db7f23af5fe584477093612179cf566b
--- /dev/null
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <malloc.h>
+
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESDHC_BOOT_IMAGE_SIZE 0x48
+#define ESDHC_BOOT_IMAGE_ADDR 0x50
+#define MBRDBR_BOOT_SIG_55 0x1fe
+#define MBRDBR_BOOT_SIG_AA 0x1ff
+#define CONFIG_CFG_DATA_SECTOR 0
+
+/*
+ * The main entry for mmc booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from mmc into SDRAM and starts it from there.
+ */
+
+void __noreturn mmc_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+ uint blk_start, blk_cnt, err;
+ u32 blklen;
+ uchar *tmp_buf;
+ uchar val;
+ uint i, byte_num;
+ u32 offset, code_len;
+ struct mmc *mmc;
+
+ mmc = find_mmc_device(0);
+ if (!mmc) {
+ puts("spl: mmc device not found!!\n");
+ hang();
+ }
+
+ blklen = mmc->read_bl_len;
+ tmp_buf = malloc(blklen);
+ if (!tmp_buf) {
+ puts("spl: malloc memory failed!!\n");
+ hang();
+ }
+ memset(tmp_buf, 0, blklen);
+
+ /*
+ * Read source addr from sd card
+ */
+ err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
+ if (err != 1) {
+ puts("spl: mmc read failed!!\n");
+ free(tmp_buf);
+ hang();
+ }
+
+ val = *(tmp_buf + MBRDBR_BOOT_SIG_55);
+ if (0x55 != val) {
+ puts("spl: mmc signature is not valid!!\n");
+ free(tmp_buf);
+ hang();
+ }
+ val = *(tmp_buf + MBRDBR_BOOT_SIG_AA);
+ if (0xAA != val) {
+ puts("spl: mmc signature is not valid!!\n");
+ free(tmp_buf);
+ hang();
+ }
+
+ byte_num = 4;
+ offset = 0;
+ for (i = 0; i < byte_num; i++) {
+ val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i);
+ offset = (offset << 8) + val;
+ }
+ offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
+ /* Get the code size from offset 0x48 */
+ byte_num = 4;
+ code_len = 0;
+ for (i = 0; i < byte_num; i++) {
+ val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i);
+ code_len = (code_len << 8) + val;
+ }
+ code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS;
+ /*
+ * Load U-Boot image from mmc into RAM
+ */
+ blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
+ err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
+ (uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
+ if (err != blk_cnt) {
+ puts("spl: mmc read failed!!\n");
+ free(tmp_buf);
+ hang();
+ }
+
+ /*
+ * Clean d-cache and invalidate i-cache, to
+ * make sure that no stale data is executed.
+ */
+ flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE);
+
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START;
+ (*uboot)();
+}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 4da8db9bed2d1ef0e4f4d4b3460d8689eeeeb9e8..55026759ede4d41cbb26e2096a965e87e9b812b6 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1483,7 +1483,9 @@ int mmc_initialize(bd_t *bis)
if (board_mmc_init(bis) < 0)
cpu_mmc_init(bis);
+#ifndef CONFIG_SPL_BUILD
print_mmc_devices(',');
+#endif
do_preinit();
return 0;
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index e27e0b7050b002f5dbe1aab888f2c9060164f4c4..366dee667062d192b63af1f40556d61f77a8d460 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -23,6 +23,7 @@ COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
+COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o
else # not spl
diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c
index 7e5599ac634b4dd784efc38da4be4da3976418c3..a7476b49bb0e5688d2b84fccb10f7cf6f14cac7a 100644
--- a/drivers/mtd/nand/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/fsl_elbc_spl.c
@@ -34,7 +34,11 @@ static void nand_wait(void)
}
}
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -113,6 +117,15 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
return 0;
}
+/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+ nand_load_image(offs, uboot_size, vdst)
+#endif
+
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
@@ -124,17 +137,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index e537fcf54c879e32bf61494a97e5a301e67e4715..191138ad188edaca986b3c8feda9233b8b6c7c3f 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -11,6 +11,7 @@ LIB := $(obj)libspi_flash.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
+COBJS-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..6263d8c2217e5385bce3f3778b6c774215c0002b
--- /dev/null
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi_flash.h>
+#include <malloc.h>
+
+#define ESPI_BOOT_IMAGE_SIZE 0x48
+#define ESPI_BOOT_IMAGE_ADDR 0x50
+#define CONFIG_CFG_DATA_SECTOR 0
+
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+void spi_boot(void)
+{
+ void (*uboot)(void) __noreturn;
+ u32 offset, code_len;
+ unsigned char *buf = NULL;
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (flash == NULL) {
+ puts("\nspi_flash_probe failed");
+ hang();
+ }
+
+ /*
+ * Load U-Boot image from SPI flash into RAM
+ */
+ buf = malloc(flash->page_size);
+ if (buf == NULL) {
+ puts("\nmalloc failed");
+ hang();
+ }
+ memset(buf, 0, flash->page_size);
+
+ spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR,
+ flash->page_size, (void *)buf);
+ offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
+ /* Skip spl code */
+ offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ /* Get the code size from offset 0x48 */
+ code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
+ /* Skip spl code */
+ code_len = code_len - CONFIG_SPL_MAX_SIZE;
+ /* copy code to DDR */
+ spi_flash_read(flash, offset, code_len,
+ (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+ /*
+ * Jump to U-Boot image
+ */
+ flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
+ uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+ (*uboot)();
+}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 9814395b930b1ce1d2c5043dc22957fcd6ebd1a6..5d5055ff38698c1a88ca4279be16b64333e873ab 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -555,12 +555,14 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
goto err_manufacturer_probe;
}
#endif
+#ifndef CONFIG_SPL_BUILD
printf("SF: Detected %s with page size ", flash->name);
print_size(flash->sector_size, ", total ");
print_size(flash->size, "");
if (flash->memory_map)
printf(", mapped at %p", flash->memory_map);
puts("\n");
+#endif
#ifndef CONFIG_SPI_FLASH_BAR
if (flash->size > SPI_FLASH_16MB_BOUN) {
puts("SF: Warning - Only lower 16MiB accessible,");
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 422c2c691ed31216ae60c2e2b0768bc251ce464a..cb099cd84962fa7ba09da632683c1fd8622466ff 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -341,7 +341,9 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
mac->init_mac(mac);
/* For some reason we need to set SPEED_100 */
- if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode)
+ if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
+ (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
+ mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
/* init bmi rx port, IM mode and disable */
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 144e109fd0336ec3a812ee53592afe94c2c9472a..592a67f2a58536ef2712b37150a739888e97f587 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -90,6 +90,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index 10c141fa2634b0d266c6278d63966b1fc629ac29..6253f22f75de8b938c7aeb25db8e0ae958aae49a 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -114,7 +114,45 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ break;
+ }
+
+ /* handle QSGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ /* check lane G on SerDes1 */
+ if (is_serdes_configured(QSGMII_FM1_A))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ /* check lane C on SerDes1 */
+ if (is_serdes_configured(QSGMII_FM1_B))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ case FM2_DTSEC1:
+ case FM2_DTSEC2:
+ case FM2_DTSEC3:
+ case FM2_DTSEC4:
+ /* check lane G on SerDes2 */
+ if (is_serdes_configured(QSGMII_FM2_A))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ case FM2_DTSEC5:
+ case FM2_DTSEC6:
+ case FM2_DTSEC9:
+ case FM2_DTSEC10:
+ /* check lane C on SerDes2 */
+ if (is_serdes_configured(QSGMII_FM2_B))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ default:
+ break;
}
return PHY_INTERFACE_MODE_NONE;
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index c883d3cac068e02cfb3a8831cd06fc78fc5130c6..7c845827627bc2a276e326f7119fab2c485fffc9 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -75,7 +75,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
/* Set eSPI BRG clock source */
get_sys_info(&sysinfo);
- spibrg = sysinfo.freqSystemBus / 2;
+ spibrg = sysinfo.freq_systembus / 2;
fsl->div16 = 0;
if ((spibrg / max_hz) > 32) {
fsl->div16 = ESPI_CSMODE_DIV16;
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6c6ce58fb88709401393424363891a3d9bd3ba7a..ddcbfa6a264c40bfc90282d60579cd4f1c5c6d58 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -24,7 +24,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index d1ce9fdc8d8436a327acea07adbfcaba6e8d7dfa..edece1f9b57a4bfe85094351502fb29b2953e0d0 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -16,42 +16,105 @@
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#define CONFIG_NAND_FSL_ELBC
#ifdef CONFIG_NAND
#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SYS_TEXT_BASE 0x00201000
-#define CONFIG_SPL_TEXT_BASE 0xfffff000
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
/* High Level Configuration Options */
@@ -225,11 +288,11 @@
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
/* NAND flash config */
@@ -291,6 +354,43 @@
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
/*
* Serial Port
*/
@@ -299,7 +399,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -521,7 +621,7 @@
/*
* Environment
*/
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
@@ -530,14 +630,20 @@
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 9657228449f00249498bffecfa561dfe2910d885..5f0c4fb254be812c329563ca24539cdc4ee853b1 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -172,7 +172,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
diff --git a/include/e500.h b/include/e500.h
index 0ff8e89a1e345f8274f3c83da715f301ca1ce0a8..0c2432657be189546c20032204af0dd1ab0b83db 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -10,19 +10,19 @@
typedef struct
{
- unsigned long freqProcessor[CONFIG_MAX_CPUS];
- unsigned long freqSystemBus;
- unsigned long freqDDRBus;
- unsigned long freqLocalBus;
- unsigned long freqQE;
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+ unsigned long freq_ddrbus;
+ unsigned long freq_localbus;
+ unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
- unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
+ unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- unsigned long freqQMAN;
+ unsigned long freq_qman;
#endif
#ifdef CONFIG_SYS_DPAA_PME
- unsigned long freqPME;
+ unsigned long freq_pme;
#endif
} MPC85xx_SYS_INFO;
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 2c97398f4eafe84325be0727469266d70be52ecb..89bcbd1700ac7b62d4fcc06304177a176180aef3 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -182,5 +182,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd);
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
#endif /* CONFIG_FSL_ESDHC */
+void __noreturn mmc_boot(void);
#endif /* __FSL_ESDHC_H__ */
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 31e83f2cc9213377fc55ae8473c96e9e0c40fd47..9fe47480325354270ec9b5cee7194b7d1025464d 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -41,9 +41,9 @@
#ifndef __ASSEMBLY__
typedef struct {
- unsigned long freqProcessor;
- unsigned long freqSystemBus;
- unsigned long freqLocalBus;
+ unsigned long freq_processor;
+ unsigned long freq_systembus;
+ unsigned long freq_localbus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable
diff --git a/spl/Makefile b/spl/Makefile
index 02f4860755820c4f26b04869fdb77a41c4f54e00..339e5e897115815162ba999790f168a3a58ea80f 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -17,10 +17,22 @@
CONFIG_SPL_BUILD := y
export CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TPL_BUILD),y)
+export CONFIG_TPL_BUILD
+SPL_BIN := u-boot-tpl
+else
+SPL_BIN := u-boot-spl
+endif
+
include $(TOPDIR)/config.mk
# We want the final binaries in this directory
+ifeq ($(CONFIG_TPL_BUILD),y)
+obj := $(OBJTREE)/tpl/
+SPLTREE := $(TPLTREE)
+else
obj := $(OBJTREE)/spl/
+endif
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n)
@@ -50,6 +62,9 @@ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
ifeq ($(CPU),mpc85xx)
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ifdef CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+endif
endif
ifeq ($(CPU),mpc86xx)
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
@@ -158,7 +173,7 @@ $(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin
$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
-ALL-y += $(obj)u-boot-spl.bin
+ALL-y += $(obj)$(SPL_BIN).bin
ifdef CONFIG_SAMSUNG
ALL-y += $(obj)$(BOARD)-spl.bin
@@ -172,15 +187,15 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
$(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
endif
-$(obj)u-boot-spl.bin: $(obj)u-boot-spl
+$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
$(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
GEN_UBOOT = \
cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
- -Map u-boot-spl.map -o u-boot-spl
+ -Map $(SPL_BIN).map -o $(SPL_BIN)
-$(obj)u-boot-spl: depend $(START) $(LIBS) $(obj)u-boot-spl.lds
+$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds
$(GEN_UBOOT)
$(START): depend