From 8a65f69c9cef09aebc20aca98a4ddbf2b4829995 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <contact@paulk.fr>
Date: Sat, 16 May 2015 19:52:11 +0200
Subject: [PATCH] sunxi: Cache line size definition

Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.

This is required to e.g. enable USB gadget.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 include/configs/sunxi-common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index f80f006e3db..d829899c07d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -66,6 +66,9 @@
 # define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 #endif
 
+/* CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
-- 
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