From 9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32 Mon Sep 17 00:00:00 2001
From: Dirk Behme <dirk.behme@googlemail.com>
Date: Sun, 31 May 2009 12:44:42 +0200
Subject: [PATCH] OMAP3: Fix CKE1 MUX setting to allow self-refresh
The Beagle rev Cx and Overo boards are using both SDRC CSes. The MUX
setting is needed for the second CS clock signal to allow the 2 RAM
parts to be put in self-refresh correctly. This also works on rev B
Beagle boards with 128M of RAM.
From: Steve Sakoman <steve@sakoman.com>
From: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
---
board/omap3/beagle/beagle.h | 2 +-
board/omap3/overo/overo.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h
index 324ec66fbec..3a0f907d77a 100644
--- a/board/omap3/beagle/beagle.h
+++ b/board/omap3/beagle/beagle.h
@@ -371,7 +371,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
#define MUX_BEAGLE_C() \
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h
index b595f6ac3e1..0b59120a300 100644
--- a/board/omap3/overo/overo.h
+++ b/board/omap3/overo/overo.h
@@ -376,6 +376,6 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
#endif
--
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