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Commit aa0d99fc authored by Alison Wang's avatar Alison Wang Committed by jason
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ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x 


Signed-off-by: default avatarAlison Wang <b18965@freescale.com>
parent 32dbaafa
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arch/m68k/cpu/mcf532x/cpu.c
+ 18
− 15
View file @ aa0d99fc
......@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -31,15 +31,16 @@
#include <netdev.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
rcm->rcr |= RCM_RCR_SOFTRST;
setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
......@@ -47,14 +48,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int checkcpu(void)
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
msk = (in_be16(&ccm->cir) >> 6);
ver = (in_be16(&ccm->cir) & 0x003f);
switch (msk) {
#ifdef CONFIG_MCF5301x
case 0x78:
......@@ -115,18 +116,20 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdp->sr = 0x5555; /* Count register */
wdp->sr = 0xAAAA; /* Count register */
/* Count register */
out_be16(&wdp->sr, 0x5555);
out_be16(&wdp->sr, 0xaaaa);
}
int watchdog_disable(void)
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
/* halted watchdog timer */
setbits_be16(&wdp->cr, WTM_WCR_HALTED);
puts("WATCHDOG:disabled\n");
return (0);
......@@ -134,18 +137,18 @@ int watchdog_disable(void)
int watchdog_init(void)
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
wdp->mr = (wdog_module / 8192);
out_be16(&wdp->mr, wdog_module / 8192);
#else
wdp->mr = (wdog_module / 4096);
out_be16(&wdp->mr, wdog_module / 4096);
#endif
wdp->cr = WTM_WCR_EN;
out_be16(&wdp->cr, WTM_WCR_EN);
puts("WATCHDOG:enabled\n");
return (0);
......
arch/m68k/cpu/mcf532x/cpu_init.c
+ 160
− 144
View file @ aa0d99fc
......@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -28,6 +28,7 @@
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
......@@ -38,72 +39,68 @@
#ifdef CONFIG_MCF5301x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
/*wdog->cr = 0; */
#endif
scm1->mpr = 0x77777777;
scm1->pacra = 0;
scm1->pacrb = 0;
scm1->pacrc = 0;
scm1->pacrd = 0;
scm1->pacre = 0;
scm1->pacrf = 0;
scm1->pacrg = 0;
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
gpio->par_cs |= GPIO_PAR_CS0_CS0;
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
gpio->par_cs |= GPIO_PAR_CS1_CS1;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
#endif
icache_enable();
......@@ -113,21 +110,21 @@ void cpu_init_f(void)
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
rtcex->gocu = CONFIG_SYS_RTC_CNT;
rtcex->gocl = CONFIG_SYS_RTC_SETUP;
out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
#endif
#ifdef CONFIG_MCFFEC
if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
ccm->misccr |= CCM_MISCCR_FECM;
setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
else
ccm->misccr &= ~CCM_MISCCR_FECM;
clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
#endif
return (0);
......@@ -135,41 +132,52 @@ int cpu_init_r(void)
void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
setbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
gpio->par_simp1h &=
~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
GPIO_PAR_SIMP1H_VEN1_UNMASK);
gpio->par_simp1h |=
(GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
clrbits_8(&gpio->par_simp1h,
GPIO_PAR_SIMP1H_DATA1_UNMASK |
GPIO_PAR_SIMP1H_VEN1_UNMASK);
setbits_8(&gpio->par_simp1h,
GPIO_PAR_SIMP1H_DATA1_U1TXD |
GPIO_PAR_SIMP1H_VEN1_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
gpio->par_ssih &=
~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
gpio->par_ssih |=
(GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
clrbits_8(&gpio->par_ssih,
GPIO_PAR_SSIH_RXD_UNMASK |
GPIO_PAR_SSIH_TXD_UNMASK);
setbits_8(&gpio->par_ssih,
GPIO_PAR_SSIH_RXD_U1RXD |
GPIO_PAR_SSIH_TXD_U1TXD);
#endif
break;
case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
setbits_8(&gpio->par_uart,
GPIO_PAR_UART_U2TXD |
GPIO_PAR_UART_U2RXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
gpio->par_dspih &=
~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
gpio->par_dspih |=
(GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
clrbits_8(&gpio->par_dspih,
GPIO_PAR_DSPIH_SIN_UNMASK |
GPIO_PAR_DSPIH_SOUT_UNMASK);
setbits_8(&gpio->par_dspih,
GPIO_PAR_DSPIH_SIN_U2RXD |
GPIO_PAR_DSPIH_SOUT_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
clrbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SDA_UNMASK |
GPIO_PAR_FECI2C_SCL_UNMASK);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SDA_U2TXD |
GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
break;
}
......@@ -178,30 +186,30 @@ void uart_port_conf(int port)
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_fec |=
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
setbits_8(&gpio->par_fec,
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
} else {
gpio->par_fec |=
GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
setbits_8(&gpio->par_fec,
GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
}
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_fec &=
~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
clrbits_8(&gpio->par_fec,
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
} else {
gpio->par_fec &=
~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
clrbits_8(&gpio->par_fec,
GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
}
}
return 0;
......@@ -212,80 +220,81 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
wdog_t *wdog = (wdog_t *) MMAP_WDOG;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
wdog->cr = 0;
out_be16(&wdog->cr, 0);
#endif
scm1->mpr0 = 0x77777777;
scm2->pacra = 0;
scm2->pacrb = 0;
scm2->pacrc = 0;
scm2->pacrd = 0;
scm2->pacre = 0;
scm2->pacrf = 0;
scm2->pacrg = 0;
scm1->pacrh = 0;
out_be32(&scm1->mpr0, 0x77777777);
out_be32(&scm2->pacra, 0);
out_be32(&scm2->pacrb, 0);
out_be32(&scm2->pacrc, 0);
out_be32(&scm2->pacrd, 0);
out_be32(&scm2->pacre, 0);
out_be32(&scm2->pacrf, 0);
out_be32(&scm2->pacrg, 0);
out_be32(&scm1->pacrh, 0);
/* Port configuration */
gpio->par_cs = 0;
out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2;
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3;
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
icache_enable();
......@@ -301,30 +310,35 @@ int cpu_init_r(void)
void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
clrbits_be16(&gpio->par_uart,
GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
setbits_be16(&gpio->par_uart,
GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
break;
case 1:
gpio->par_uart &=
~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
gpio->par_uart |=
(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
clrbits_be16(&gpio->par_uart,
GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
setbits_be16(&gpio->par_uart,
GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
break;
case 2:
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio->par_timer &= 0x0F;
gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
clrbits_8(&gpio->par_timer, 0xf0);
setbits_8(&gpio->par_timer,
GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
gpio->par_feci2c &= 0xFF00;
gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
clrbits_8(&gpio->par_feci2c, 0x00ff);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
gpio->par_ssi &= 0xF0FF;
gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
clrbits_be16(&gpio->par_ssi, 0x0f00);
setbits_be16(&gpio->par_ssi,
GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
#endif
break;
}
......@@ -333,16 +347,18 @@ void uart_port_conf(int port)
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
setbits_8(&gpio->par_fec,
GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
} else {
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
clrbits_8(&gpio->par_fec,
GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
clrbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
}
return 0;
}
......
arch/m68k/cpu/mcf532x/interrupts.c
+ 8
− 7
View file @ aa0d99fc
/*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -25,14 +25,15 @@
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
intp->imrl0 |= 0xFFFFFFFF;
setbits_be32(&intp->imrh0, 0xffffffff);
setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
......@@ -41,9 +42,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
arch/m68k/cpu/mcf532x/speed.c
+ 40
− 37
View file @ aa0d99fc
......@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -29,6 +29,7 @@
#include <asm/processor.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -65,13 +66,13 @@ DECLARE_GLOBAL_DATA_PTR;
/* Get the value of the current system clock */
int get_sys_clock(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
ccm_t *ccm = (ccm_t *)(MMAP_CCM);
pll_t *pll = (pll_t *)(MMAP_PLL);
int divider;
/* Test to see if device is in LIMP mode */
if (ccm->misccr & CCM_MISCCR_LIMP) {
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
#ifdef CONFIG_MCF5301x
return (FREF / (3 * (1 << divider)));
#endif
......@@ -80,14 +81,14 @@ int get_sys_clock(void)
#endif
} else {
#ifdef CONFIG_MCF5301x
u32 pfdr = (pll->pcr & 0x3F) + 1;
u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
return (((FREF * pfdr) / refdiv) / busdiv);
#endif
#ifdef CONFIG_MCF532x
return ((FREF * pll->pfdr) / (BUSDIV * 4));
return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
#endif
}
}
......@@ -103,7 +104,7 @@ int get_sys_clock(void)
*/
int clock_limp(int div)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
ccm_t *ccm = (ccm_t *)(MMAP_CCM);
u32 temp;
/* Check bounds of divider */
......@@ -113,12 +114,12 @@ int clock_limp(int div)
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't overwrite the value */
temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
/* Apply the divider to the system clock */
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
ccm->misccr |= CCM_MISCCR_LIMP;
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
return (FREF / (3 * (1 << div)));
}
......@@ -126,14 +127,15 @@ int clock_limp(int div)
/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
ccm_t *ccm = (ccm_t *)(MMAP_CCM);
int fout;
/* Exit LIMP mode */
ccm->misccr &= (~CCM_MISCCR_LIMP);
clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
/* Wait for PLL to lock */
while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
;
fout = get_sys_clock();
......@@ -153,10 +155,10 @@ int clock_exit_limp(void)
int clock_pll(int fsys, int flags)
{
#ifdef CONFIG_MCF532x
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
#endif
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
pll_t *pll = (pll_t *)(MMAP_PLL);
int fref, temp, fout, mfd;
u32 i;
......@@ -165,13 +167,13 @@ int clock_pll(int fsys, int flags)
if (fsys == 0) {
/* Return current PLL output */
#ifdef CONFIG_MCF5301x
u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
mfd = (pll->pcr & 0x3F) + 1;
u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
return (fref * mfd) / busdiv;
#endif
#ifdef CONFIG_MCF532x
mfd = pll->pfdr;
mfd = in_8(&pll->pfdr);
return (fref * mfd / (BUSDIV * 4));
#endif
......@@ -211,8 +213,8 @@ int clock_pll(int fsys, int flags)
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
if (sdram->ctrl & SDRAMC_SDCR_REF)
sdram->ctrl &= ~SDRAMC_SDCR_CKE;
if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
/*
* Initialize the PLL to generate the new system clock frequency.
......@@ -223,35 +225,36 @@ int clock_pll(int fsys, int flags)
clock_limp(DEFAULT_LPD);
#ifdef CONFIG_MCF5301x
pll->pdr =
PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
PLL_PDR_OUTDIV2(BUSDIV - 1) |
PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
PLL_PDR_OUTDIV4(USBDIV - 1);
pll->pcr &= PLL_PCR_FBDIV_UNMASK;
pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
out_be32(&pll->pdr,
PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
PLL_PDR_OUTDIV2(BUSDIV - 1) |
PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
PLL_PDR_OUTDIV4(USBDIV - 1));
clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
#endif
#ifdef CONFIG_MCF532x
/* Reprogram PLL for desired fsys */
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
out_8(&pll->podr,
PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
pll->pfdr = mfd;
out_8(&pll->pfdr, mfd);
#endif
/* Exit LIMP mode */
clock_exit_limp();
/* Return the SDRAM to normal operation if it is in use. */
if (sdram->ctrl & SDRAMC_SDCR_REF)
sdram->ctrl |= SDRAMC_SDCR_CKE;
if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
#ifdef CONFIG_MCF532x
/*
* software workaround for SDRAM opeartion after exiting LIMP
* mode errata
*/
*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
#endif
/* wait for DQS logic to relock */
......
board/freescale/m53017evb/m53017evb.c
+ 15
− 13
View file @ aa0d99fc
......@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
......@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_MODE;
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
......
board/freescale/m5329evb/m5329evb.c
+ 15
− 13
View file @ aa0d99fc
......@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
......@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
sdram->mode = CONFIG_SYS_SDRAM_MODE;
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
......
board/freescale/m5329evb/nand.c
+ 7
− 7
View file @ aa0d99fc
......@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
gpio->pclrr_timer = 0;
gpio->podr_timer = 0;
clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
setbits_8(&gpio->pddr_timer, 0x08);
setbits_8(&gpio->ppd_timer, 0x08);
out_8(&gpio->pclrr_timer, 0);
out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
......
board/freescale/m5373evb/m5373evb.c
+ 15
− 13
View file @ aa0d99fc
......@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
......@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
sdram->mode = CONFIG_SYS_SDRAM_MODE;
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
......
board/freescale/m5373evb/nand.c
+ 9
− 9
View file @ aa0d99fc
......@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
......@@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
gpio->pclrr_timer = 0;
gpio->podr_timer = 0;
clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
setbits_8(&gpio->pddr_timer, 0x08);
setbits_8(&gpio->ppd_timer, 0x08);
out_8(&gpio->pclrr_timer, 0);
out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
......
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