dm: x86: baytrail: Correct PCI region 3 when driver model is used

Commit afbbd413 fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

arch/x86/cpu/cpu.c

@@ -353,6 +353,8 @@ int x86_cpu_init_f(void)
 
 		gd->arch.has_mtrr = has_mtrr();
 	}
+	/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+	gd->pci_ram_top = 0x80000000U;
 
 	/* Configure fixed range MTRRs for some legacy regions */
 	if (gd->arch.has_mtrr) {

drivers/pci/pci-uclass.c

@@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
 {
 	int pci_addr_cells, addr_cells, size_cells;
 	int cells_per_record;
+	phys_addr_t addr;
 	const u32 *prop;
 	int len;
 	int i;
@@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
 	}
 
 	/* Add a region for our local memory */
-	pci_set_region(hose->regions + hose->region_count++, 0, 0,
-		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+	addr = gd->ram_size;
+	if (gd->pci_ram_top && gd->pci_ram_top < addr)
+		addr = gd->pci_ram_top;
+	pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	return 0;
 }

include/asm-generic/global_data.h

@@ -93,6 +93,7 @@ typedef struct global_data {
 #endif
 #ifdef CONFIG_PCI
 	struct pci_controller *hose;	/* PCI hose for early use */
+	phys_addr_t pci_ram_top;	/* top of region accessible to PCI */
 #endif
 #ifdef CONFIG_PCI_BOOTDELAY
 	int pcidelay_done;