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Commit d193c1b6 authored by Albert ARIBAUD's avatar Albert ARIBAUD
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Merge remote-tracking branch 'u-boot-imx/master'

parents 651eb732 1d9b0332
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with 221 additions and 195 deletions
Makefile
+ 3
− 5
View file @ d193c1b6
......@@ -306,11 +306,8 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),mx5)
LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
endif
ifeq ($(SOC),mx6)
LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
ifeq ($(SOC),s5pc1xx)
......@@ -776,6 +773,7 @@ clean:
$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
$(obj)tools/mk{smdk5250,}spl \
$(obj)tools/mxsboot \
$(obj)tools/ncb $(obj)tools/ubsha1
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
$(obj)board/matrix_vision/*/bootscript.img \
......
arch/arm/cpu/arm1136/mx31/generic.c
+ 7
− 5
View file @ d193c1b6
......@@ -22,6 +22,7 @@
*/
#include <common.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
......@@ -30,16 +31,17 @@
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
u32 mfi = GET_PLL_MFI(reg);
u32 mfn = GET_PLL_MFN(reg);
s32 mfn = GET_PLL_MFN(reg);
u32 mfd = GET_PLL_MFD(reg);
u32 pd = GET_PLL_PD(reg);
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
(mfd * pd)) << 10;
return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
mfd * pd);
}
static u32 mx31_get_mpl_dpdgck_clk(void)
......@@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
u32 infreq;
if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
infreq = CONFIG_MX31_CLK32 * 1024;
infreq = MXC_CLK32 * 1024;
else
infreq = CONFIG_MX31_HCLK_FREQ;
infreq = MXC_HCLK;
return mx31_decode_pll(readl(CCM_MPCTL), infreq);
}
......
arch/arm/cpu/arm1136/mx31/timer.c
+ 8
− 8
View file @ d193c1b6
......@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <div64.h>
#include <watchdog.h>
#include <asm/io.h>
......@@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX31_CLK32);
do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX31_CLK32;
time *= MXC_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX31_CLK32 + 999999;
us = us * MXC_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
/ CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / MXC_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
......@@ -128,7 +128,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
......@@ -159,7 +159,7 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
return CONFIG_MX31_CLK32;
return MXC_CLK32;
}
void reset_cpu(ulong addr)
......
arch/arm/cpu/arm1136/mx35/generic.c
+ 35
− 55
View file @ d193c1b6
......@@ -24,6 +24,7 @@
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
......@@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0)
static u32 decode_pll(u32 reg, u32 infreq)
{
u32 mfi = (reg >> 10) & 0xf;
u32 mfn = reg & 0x3f;
u32 mfd = (reg >> 16) & 0x3f;
s32 mfn = reg & 0x3ff;
u32 mfd = (reg >> 16) & 0x3ff;
u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
mfd * pd);
}
static u32 get_mcu_main_clk(void)
......@@ -146,9 +149,7 @@ static u32 get_mcu_main_clk(void)
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
fi *=
decode_pll(readl(&ccm->mpctl),
CONFIG_MX35_HCLK_FREQ);
fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
return fi / (arm_div * fd);
}
......@@ -171,17 +172,14 @@ static u32 get_ipg_per_clk(void)
u32 pdr4 = readl(&ccm->pdr4);
u32 div;
if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
div = (CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_PER0_PRDF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
(CCM_GET_DIVIDER(pdr4,
div = CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
} else {
div = CCM_GET_DIVIDER(pdr0,
MXC_CCM_PDR0_PER_PODF_MASK,
MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
freq /= get_ahb_div(pdr0);
div *= get_ahb_div(pdr0);
}
return freq / div;
}
......@@ -193,25 +191,20 @@ u32 imx_get_uartclk(void)
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr4 = readl(&ccm->pdr4);
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
freq = get_mcu_main_clk();
} else {
freq = decode_pll(readl(&ccm->ppctl),
CONFIG_MX35_HCLK_FREQ);
}
freq /= ((CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PRDF_MASK,
MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
(CCM_GET_DIVIDER(pdr4,
else
freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
return freq;
}
unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
{
u32 nfc_pdf, hsp_podf;
u32 pll, ret_val = 0, usb_prdf, usb_podf;
u32 pll, ret_val = 0, usb_podf;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
......@@ -255,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
ret_val = pll / (nfc_pdf + 1);
break;
case USB_CLK:
usb_prdf = (reg4 >> 25) & 0x7;
usb_podf = (reg4 >> 22) & 0x7;
if (reg4 & 0x200) {
usb_podf = (reg4 >> 22) & 0x3F;
if (reg4 & 0x200)
pll = get_mcu_main_clk();
} else {
pll = decode_pll(readl(&ccm->ppctl),
CONFIG_MX35_HCLK_FREQ);
}
else
pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
ret_val = pll / (usb_podf + 1);
break;
default:
printf("Unknown clock: %d\n", clk);
......@@ -287,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
case UART2_BAUD:
case UART3_BAUD:
clk_sel = mpdr3 & (1 << 14);
pre_pdf = (mpdr4 >> 13) & 0x7;
pdf = (mpdr4 >> 10) & 0x7;
pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
((pre_pdf + 1) * (pdf + 1));
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
pdf = mpdr2 & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case SSI2_BAUD:
......@@ -306,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
pdf = (mpdr2 >> 8) & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
pre_pdf = (mpdr2 >> 16) & 0x7;
pdf = (mpdr2 >> 19) & 0x7;
pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
((pre_pdf + 1) * (pdf + 1));
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
......@@ -323,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
pdf = (pre_pdf >> 22) & 0x3F;
pre_pdf = (pre_pdf >> 28) & 0x7;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case ESDHC1_CLK:
clk_sel = mpdr3 & 0x40;
pre_pdf = mpdr3 & 0x7;
pdf = (mpdr3>>3) & 0x7;
pdf = mpdr3 & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
((pre_pdf + 1) * (pdf + 1));
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC2_CLK:
clk_sel = mpdr3 & 0x40;
pre_pdf = (mpdr3 >> 8) & 0x7;
pdf = (mpdr3 >> 11) & 0x7;
pdf = (mpdr3 >> 8) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
((pre_pdf + 1) * (pdf + 1));
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC3_CLK:
clk_sel = mpdr3 & 0x40;
pre_pdf = (mpdr3 >> 16) & 0x7;
pdf = (mpdr3 >> 19) & 0x7;
pdf = (mpdr3 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
((pre_pdf + 1) * (pdf + 1));
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SPDIF_CLK:
clk_sel = mpdr3 & 0x400000;
pre_pdf = (mpdr3 >> 29) & 0x7;
pdf = (mpdr3 >> 23) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
......
arch/arm/cpu/arm1136/mx35/timer.c
+ 28
− 18
View file @ d193c1b6
......@@ -27,6 +27,7 @@
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, TIMER_FREQ_HZ);
do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
static inline unsigned long long us_to_tick(unsigned long long us)
{
usec *= TIMER_FREQ_HZ;
do_div(usec, 1000000);
us = us * MXC_CLK32 + 999999;
do_div(us, 1000000);
return usec;
return us;
}
/*
* nothing really to do with interrupts, just starts up a counter.
* The 32KHz 32-bit timer overruns in 134217 seconds
*/
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &gpt->ctrl);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre);
/* Freerun Mode, PERCLK1 input */
writel(readl(&gpt->ctrl) |
GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
&gpt->ctrl);
writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
return 0;
}
......@@ -101,7 +111,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
......@@ -132,5 +142,5 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
return TIMER_FREQ_HZ;
return MXC_CLK32;
}
arch/arm/cpu/arm926ejs/mx25/generic.c
+ 1
− 1
View file @ d193c1b6
......@@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
static ulong imx_get_mpllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = 24000000;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
......
arch/arm/cpu/arm926ejs/mx25/timer.c
+ 8
− 8
View file @ d193c1b6
......@@ -40,6 +40,7 @@
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX25_CLK32);
do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX25_CLK32;
time *= MXC_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX25_CLK32 + 999999;
us = us * MXC_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32)
#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / MXC_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
......@@ -144,7 +144,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
......@@ -177,6 +177,6 @@ ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CONFIG_MX25_CLK32;
tbclk = MXC_CLK32;
return tbclk;
}
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+ 5
− 3
View file @ d193c1b6
......@@ -38,12 +38,14 @@
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
* code simple, it doesn't take rolling into consideration.
*/
#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
void early_delay(int delay)
{
uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
st += delay;
while (st > readl(HW_DIGCTRL_MICROSECONDS))
while (st > readl(&digctl_regs->hw_digctl_microseconds))
;
}
......
arch/arm/cpu/armv7/imx-common/Makefile → arch/arm/imx-common/Makefile
+ 3
− 1
View file @ d193c1b6
......@@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
COBJS-y = iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS := $(sort $(COBJS-y))
......
arch/arm/cpu/armv7/imx-common/cpu.c → arch/arm/imx-common/cpu.c
+ 0
− 0
View file @ d193c1b6
File moved
arch/arm/cpu/armv7/imx-common/speed.c → arch/arm/imx-common/speed.c
+ 0
− 0
View file @ d193c1b6
File moved
arch/arm/cpu/armv7/imx-common/timer.c → arch/arm/imx-common/timer.c
+ 0
− 0
View file @ d193c1b6
File moved
arch/arm/include/asm/arch-mx25/clock.h
+ 14
− 0
View file @ d193c1b6
......@@ -26,6 +26,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#include <common.h>
#ifdef CONFIG_MX25_HCLK_FREQ
#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_MX25_CLK32
#define MXC_CLK32 CONFIG_MX25_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_CSI_CLK,
MXC_EPIT_CLK,
......
arch/arm/include/asm/arch-mx31/clock.h
+ 14
− 0
View file @ d193c1b6
......@@ -24,6 +24,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#include <common.h>
#ifdef CONFIG_MX31_HCLK_FREQ
#define MXC_HCLK CONFIG_MX31_HCLK_FREQ
#else
#define MXC_HCLK 26000000
#endif
#ifdef CONFIG_MX31_CLK32
#define MXC_CLK32 CONFIG_MX31_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_ARM_CLK,
MXC_IPG_CLK,
......
arch/arm/include/asm/arch-mx35/clock.h
+ 14
− 0
View file @ d193c1b6
......@@ -24,6 +24,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#include <common.h>
#ifdef CONFIG_MX35_HCLK_FREQ
#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_MX35_CLK32
#define MXC_CLK32 CONFIG_MX35_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_ARM_CLK,
MXC_AHB_CLK,
......
arch/arm/include/asm/arch-mx35/crm_regs.h
+ 19
− 29
View file @ d193c1b6
......@@ -32,8 +32,8 @@
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
#define MXC_CCM_CCMR_ROMW_OFFSET 18
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
#define MXC_CCM_CCMR_RAMW_OFFSET 21
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21)
#define MXC_CCM_CCMR_RAMW_OFFSET 16
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
#define MXC_CCM_CCMR_LPM_OFFSET 14
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
#define MXC_CCM_CCMR_UPE (1 << 9)
......@@ -47,7 +47,7 @@
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12)
#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
#define MXC_CCM_PDR0_AUTO_CON 0x1
......@@ -62,10 +62,8 @@
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19
#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16)
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
......@@ -78,35 +76,23 @@
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19
#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16)
#define MXC_CCM_PDR3_UART_M_U (1 << 15)
#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11
#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11)
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR3_UART_M_U (1 << 14)
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8)
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3
#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3)
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7)
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25
#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25)
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22)
#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19
#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22)
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16)
#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13
#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13)
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10)
#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10)
#define MXC_CCM_PDR4_USB_M_U (1 << 9)
/* Bit definitions for RCSR */
......@@ -144,6 +130,12 @@
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
/* Bit definitions for Clock gating Register*/
#define MXC_CCM_CGR_CG_MASK 0x3
#define MXC_CCM_CGR_CG_OFF 0x0
#define MXC_CCM_CGR_CG_RUN_ON 0x1
#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2
#define MXC_CCM_CGR_CG_ON 0x3
#define MXC_CCM_CGR0_ASRC_OFFSET 0
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
#define MXC_CCM_CGR0_ATA_OFFSET 2
......@@ -251,10 +243,8 @@
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
#define MXC_CCM_COSR_CLKOEN (1 << 5)
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10)
#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10
#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13)
#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13
#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10)
#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
......
arch/arm/include/asm/arch-mx6/iomux.h
+ 62
− 62
View file @ d193c1b6
......@@ -34,21 +34,21 @@
#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19)
#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19)
#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
......@@ -63,55 +63,55 @@
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7)
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2)
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2)
#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
......
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