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Commit e5f5c4a9 authored by Albert ARIBAUD's avatar Albert ARIBAUD
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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

parents 7cb70a34 81ca8409
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.gitignore
+ 1
− 0
View file @ e5f5c4a9
......@@ -15,6 +15,7 @@
*.swp
*.patch
*.bin
*.cfgtmp
# Build tree
/build-*
......
MAINTAINERS
+ 5
− 0
View file @ e5f5c4a9
......@@ -935,6 +935,7 @@ Marek Vasut <marek.vasut@gmail.com>
palmtc xscale/pxa
vpac270 xscale/pxa
zipitz2 xscale/pxa
mx23_olinuxino i.MX23
m28evk i.MX28
sc_sps_1 i.MX28
......@@ -946,6 +947,10 @@ Matt Waddel <matt.waddel@linaro.org>
ca9x4_ct_vxp ARM ARMV7 (Quad Core)
Otavio Salvador <otavio@ossystems.com.br>
mx23evk i.MX23
Prafulla Wadaskar <prafulla@marvell.com>
aspenite ARM926EJS (ARMADA100 88AP168 SoC)
......
Makefile
+ 5
− 4
View file @ e5f5c4a9
......@@ -467,9 +467,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
......@@ -508,6 +507,7 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(obj)u-boot.ais
# Specify the target for use in elftosb call
ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
......@@ -843,7 +843,8 @@ clean:
@$(MAKE) -s -C doc/DocBook/ cleandocs
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \
-o -name '*.cfgtmp' \) -print \
| xargs rm -f
# Removes everything not needed for testing u-boot
......
arch/arm/cpu/arm926ejs/config.mk
+ 1
− 1
View file @ e5f5c4a9
......@@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
ALL-y += $(OBJTREE)/u-boot.imx
endif
arch/arm/cpu/arm926ejs/mxs/clock.c
+ 50
− 33
View file @ e5f5c4a9
/*
* Freescale i.MX28 clock setup code
* Freescale i.MX23/i.MX28 clock setup code
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
......@@ -32,16 +32,25 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
/*
* The PLL frequency is 480MHz and XTAL frequency is 24MHz
* iMX23: datasheet section 4.2
* iMX28: datasheet section 10.2
*/
#define PLL_FREQ_KHZ 480000
#define PLL_FREQ_COEF 18
/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
#define XTAL_FREQ_KHZ 24000
#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
static uint32_t mx28_get_pclk(void)
#if defined(CONFIG_MX23)
#define MXC_SSPCLK_MAX MXC_SSPCLK0
#elif defined(CONFIG_MX28)
#define MXC_SSPCLK_MAX MXC_SSPCLK3
#endif
static uint32_t mxs_get_pclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
......@@ -73,7 +82,7 @@ static uint32_t mx28_get_pclk(void)
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mx28_get_hclk(void)
static uint32_t mxs_get_hclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
......@@ -88,10 +97,10 @@ static uint32_t mx28_get_hclk(void)
return 0;
div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
return mx28_get_pclk() / div;
return mxs_get_pclk() / div;
}
static uint32_t mx28_get_emiclk(void)
static uint32_t mxs_get_emiclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
......@@ -116,11 +125,17 @@ static uint32_t mx28_get_emiclk(void)
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mx28_get_gpmiclk(void)
static uint32_t mxs_get_gpmiclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
#if defined(CONFIG_MX23)
uint8_t *reg =
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
#elif defined(CONFIG_MX28)
uint8_t *reg =
&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
#endif
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
......@@ -134,7 +149,7 @@ static uint32_t mx28_get_gpmiclk(void)
}
/* REF Path */
clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
clkfrac = readb(reg);
frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
......@@ -143,7 +158,7 @@ static uint32_t mx28_get_gpmiclk(void)
/*
* Set IO clock frequency, in kHz
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
......@@ -176,7 +191,7 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
/*
* Get IO clock, returns IO clock in kHz
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
......@@ -197,13 +212,13 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
/*
* Configure SSP clock frequency, in kHz
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp > MXC_SSPCLK3)
if (ssp > MXC_SSPCLK_MAX)
return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
......@@ -216,7 +231,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
if (xtal)
clk = XTAL_FREQ_KHZ;
else
clk = mx28_get_ioclk(ssp >> 1);
clk = mxs_get_ioclk(ssp >> 1);
if (freq > clk)
return;
......@@ -241,14 +256,14 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
/*
* Return SSP frequency, in kHz
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkreg;
uint32_t clk, tmp;
if (ssp > MXC_SSPCLK3)
if (ssp > MXC_SSPCLK_MAX)
return 0;
tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
......@@ -263,7 +278,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
if (tmp == 0)
return 0;
clk = mx28_get_ioclk(ssp >> 1);
clk = mxs_get_ioclk(ssp >> 1);
return clk / tmp;
}
......@@ -271,14 +286,14 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
/*
* Set SSP/MMC bus frequency, in kHz)
*/
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus);
const uint32_t sspclk = mxs_get_sspclk(bus);
uint32_t reg;
uint32_t divide, rate, tgtclk;
ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
ssp_regs = mxs_ssp_regs_by_bus(bus);
/*
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
......@@ -313,28 +328,30 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return mx28_get_pclk() * 1000000;
return mxs_get_pclk() * 1000000;
case MXC_GPMI_CLK:
return mx28_get_gpmiclk() * 1000000;
return mxs_get_gpmiclk() * 1000000;
case MXC_AHB_CLK:
case MXC_IPG_CLK:
return mx28_get_hclk() * 1000000;
return mxs_get_hclk() * 1000000;
case MXC_EMI_CLK:
return mx28_get_emiclk();
return mxs_get_emiclk();
case MXC_IO0_CLK:
return mx28_get_ioclk(MXC_IOCLK0);
return mxs_get_ioclk(MXC_IOCLK0);
case MXC_IO1_CLK:
return mx28_get_ioclk(MXC_IOCLK1);
return mxs_get_ioclk(MXC_IOCLK1);
case MXC_XTAL_CLK:
return XTAL_FREQ_KHZ * 1000;
case MXC_SSP0_CLK:
return mx28_get_sspclk(MXC_SSPCLK0);
return mxs_get_sspclk(MXC_SSPCLK0);
#ifdef CONFIG_MX28
case MXC_SSP1_CLK:
return mx28_get_sspclk(MXC_SSPCLK1);
return mxs_get_sspclk(MXC_SSPCLK1);
case MXC_SSP2_CLK:
return mx28_get_sspclk(MXC_SSPCLK2);
return mxs_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK:
return mx28_get_sspclk(MXC_SSPCLK3);
case MXC_XTAL_CLK:
return XTAL_FREQ_KHZ * 1000;
return mxs_get_sspclk(MXC_SSPCLK3);
#endif
}
return 0;
......
arch/arm/cpu/arm926ejs/mxs/mxs.c
+ 20
− 5
View file @ e5f5c4a9
/*
* Freescale i.MX28 common code
* Freescale i.MX23/i.MX28 common code
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
......@@ -35,6 +35,7 @@
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -196,6 +197,8 @@ static const char *get_cpu_type(void)
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX23:
return "23";
case HW_DIGCTL_CHIPID_MX28:
return "28";
default:
......@@ -210,6 +213,21 @@ static const char *get_cpu_rev(void)
uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX23:
switch (rev) {
case 0x0:
return "1.0";
case 0x1:
return "1.1";
case 0x2:
return "1.2";
case 0x3:
return "1.3";
case 0x4:
return "1.4";
default:
return "??";
}
case HW_DIGCTL_CHIPID_MX28:
switch (rev) {
case 0x1:
......@@ -276,7 +294,7 @@ int cpu_eth_init(bd_t *bis)
}
#endif
static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
{
mac[0] = 0x00;
mac[1] = 0x04; /* Use FSL vendor MAC address by default */
......@@ -285,9 +303,6 @@ static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
mac[5] += 1;
}
void mx28_adjust_mac(int dev_id, unsigned char *mac)
__attribute__((weak, alias("__mx28_adjust_mac")));
#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
#define MXS_OCOTP_MAX_TIMEOUT 1000000
......
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+ 25
− 0
View file @ e5f5c4a9
......@@ -51,12 +51,21 @@ void early_delay(int delay)
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
static const iomux_cfg_t iomux_boot[] = {
#if defined(CONFIG_MX23)
MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
#elif defined(CONFIG_MX28)
MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
#endif
};
static uint8_t mxs_get_bootmode_index(void)
......@@ -68,6 +77,21 @@ static uint8_t mxs_get_bootmode_index(void)
/* Setup IOMUX of bootmode pads to GPIO */
mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
#if defined(CONFIG_MX23)
/* Setup bootmode pins as GPIO input */
gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
/* Read bootmode pads */
bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
#elif defined(CONFIG_MX28)
/* Setup bootmode pins as GPIO input */
gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
......@@ -83,6 +107,7 @@ static uint8_t mxs_get_bootmode_index(void)
bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
#endif
for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
masked = bootmode & mxs_boot_modes[i].boot_mask;
......
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+ 100
− 18
View file @ e5f5c4a9
......@@ -27,6 +27,7 @@
#include <config.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <linux/compiler.h>
#include "mxs_init.h"
......@@ -83,16 +84,30 @@ static uint32_t dram_vals[] = {
0x06120612, 0x04320432, 0x04320432, 0x00040004,
0x00040004, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
/*
* i.MX23 DDR at 133MHz
*/
#elif defined(CONFIG_MX23)
0x01010001, 0x00010100, 0x01000101, 0x00000001,
0x00000101, 0x00000000, 0x00010000, 0x01000001,
0x00000000, 0x00000001, 0x07000200, 0x00070202,
0x02020000, 0x04040a01, 0x00000201, 0x02040000,
0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
0x02061521, 0x0000000a, 0x00080008, 0x00200020,
0x00200020, 0x00200020, 0x000003f7, 0x00000000,
0x00000000, 0x00000020, 0x00000020, 0x00c80000,
0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
0x00000101, 0x00040001, 0x00000000, 0x00000000,
0x00010000
#else
#error Unsupported memory initialization
#endif
};
void __mxs_adjust_memory_params(uint32_t *dram_vals)
__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{
}
void mxs_adjust_memory_params(uint32_t *dram_vals)
__attribute__((weak, alias("__mxs_adjust_memory_params")));
static void initialize_dram_values(void)
{
......@@ -102,19 +117,30 @@ static void initialize_dram_values(void)
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
#ifdef CONFIG_MX23
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
#endif
}
static void mxs_mem_init_clock(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
#if defined(CONFIG_MX23)
/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
const unsigned char divider = 33;
#elif defined(CONFIG_MX28)
/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
const unsigned char divider = 21;
#endif
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
/* Set fractional divider for ref_emi */
writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
/* Ungate EMI clock */
......@@ -197,10 +223,60 @@ uint32_t mxs_mem_get_size(void)
return sz;
}
void mxs_mem_init(void)
#ifdef CONFIG_MX23
static void mx23_mem_setup_vddmem(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_ILIMIT |
POWER_VDDMEMCTRL_ENABLE_LINREG |
POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
&power_regs->hw_power_vddmemctrl);
early_delay(10000);
writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_LINREG,
&power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
{
mx23_mem_setup_vddmem();
/*
* Configure the DRAM registers
*/
/* Clear START and SREFRESH bit from DRAM_CTL8 */
clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
initialize_dram_values();
/* Set START bit in DRAM_CTL16 */
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
early_delay(20000);
/* Adjust EMI port priority. */
clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
early_delay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
;
}
#endif
#ifdef CONFIG_MX28
static void mx28_mem_init(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
......@@ -208,16 +284,6 @@ void mxs_mem_init(void)
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
/* Power up PLL0 */
writel(CLKCTRL_PLL0CTRL0_POWER,
&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
early_delay(11000);
mxs_mem_init_clock();
mxs_mem_setup_vdda();
/*
* Configure the DRAM registers
*/
......@@ -236,6 +302,22 @@ void mxs_mem_init(void)
/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
}
#endif
void mxs_mem_init(void)
{
early_delay(11000);
mxs_mem_init_clock();
mxs_mem_setup_vdda();
#if defined(CONFIG_MX23)
mx23_mem_init();
#elif defined(CONFIG_MX28)
mx28_mem_init();
#endif
early_delay(10000);
......
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+ 12
− 0
View file @ e5f5c4a9
......@@ -881,11 +881,23 @@ static void mxs_setup_batt_detect(void)
early_delay(10);
}
static void mxs_ungate_power(void)
{
#ifdef CONFIG_MX23
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
#endif
}
void mxs_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_ungate_power();
mxs_power_clock2xtal();
mxs_power_clear_auto_restart();
mxs_power_set_linreg();
......
arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd 0 → 100644
+ 18
− 0
View file @ e5f5c4a9
options {
driveTag = 0x00;
flags = 0x01;
}
sources {
u_boot_spl="spl/u-boot-spl.bin";
u_boot="u-boot.bin";
}
section (0) {
load u_boot_spl > 0x0000;
load ivt (entry = 0x0014) > 0x8000;
call 0x8000;
load u_boot > 0x40000100;
call 0x40000100;
}
arch/arm/cpu/armv7/config.mk
+ 1
− 1
View file @ e5f5c4a9
......@@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
ALL-y += $(OBJTREE)/u-boot.imx
endif
arch/arm/imx-common/Makefile
+ 13
− 0
View file @ e5f5c4a9
......@@ -42,6 +42,19 @@ all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/%
mkdir -p $(dir $@)
$(CC) -E -x c $< $(CPPFLAGS) -o $@
$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
#########################################################################
# defines $(obj).depend target
......
arch/arm/include/asm/arch-mxs/clock.h
+ 9
− 5
View file @ e5f5c4a9
/*
* Freescale i.MX28 Clock
* Freescale i.MX23/i.MX28 Clock
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
......@@ -31,11 +31,13 @@ enum mxc_clock {
MXC_GPMI_CLK,
MXC_IO0_CLK,
MXC_IO1_CLK,
MXC_XTAL_CLK,
MXC_SSP0_CLK,
#ifdef CONFIG_MX28
MXC_SSP1_CLK,
MXC_SSP2_CLK,
MXC_SSP3_CLK,
MXC_XTAL_CLK,
#endif
};
enum mxs_ioclock {
......@@ -45,16 +47,18 @@ enum mxs_ioclock {
enum mxs_sspclock {
MXC_SSPCLK0 = 0,
#ifdef CONFIG_MX28
MXC_SSPCLK1,
MXC_SSPCLK2,
MXC_SSPCLK3,
#endif
};
uint32_t mxc_get_clock(enum mxc_clock clk);
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq);
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
/* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
......
arch/arm/include/asm/arch-mxs/imx-regs.h
+ 6
− 1
View file @ e5f5c4a9
/*
* Freescale i.MX28 Registers
* Freescale i.MX23/i.MX28 Registers
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
......@@ -37,6 +37,11 @@
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
#ifdef CONFIG_MX23
#include <asm/arch/regs-clkctrl-mx23.h>
#include <asm/arch/regs-power-mx23.h>
#endif
#ifdef CONFIG_MX28
#include <asm/arch/regs-clkctrl-mx28.h>
#include <asm/arch/regs-power-mx28.h>
......
arch/arm/include/asm/arch-mxs/iomux-mx23.h 0 → 100644
+ 355
− 0
View file @ e5f5c4a9
This diff is collapsed.
arch/arm/include/asm/arch-mxs/regs-apbh.h
+ 121
− 0
View file @ e5f5c4a9
......@@ -29,6 +29,87 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
mxs_reg_32(hw_apbh_ctrl2)
mxs_reg_32(hw_apbh_channel_ctrl)
union {
struct {
mxs_reg_32(hw_apbh_ch_curcmdar)
mxs_reg_32(hw_apbh_ch_nxtcmdar)
mxs_reg_32(hw_apbh_ch_cmd)
mxs_reg_32(hw_apbh_ch_bar)
mxs_reg_32(hw_apbh_ch_sema)
mxs_reg_32(hw_apbh_ch_debug1)
mxs_reg_32(hw_apbh_ch_debug2)
} ch[8];
struct {
mxs_reg_32(hw_apbh_ch0_curcmdar)
mxs_reg_32(hw_apbh_ch0_nxtcmdar)
mxs_reg_32(hw_apbh_ch0_cmd)
mxs_reg_32(hw_apbh_ch0_bar)
mxs_reg_32(hw_apbh_ch0_sema)
mxs_reg_32(hw_apbh_ch0_debug1)
mxs_reg_32(hw_apbh_ch0_debug2)
mxs_reg_32(hw_apbh_ch1_curcmdar)
mxs_reg_32(hw_apbh_ch1_nxtcmdar)
mxs_reg_32(hw_apbh_ch1_cmd)
mxs_reg_32(hw_apbh_ch1_bar)
mxs_reg_32(hw_apbh_ch1_sema)
mxs_reg_32(hw_apbh_ch1_debug1)
mxs_reg_32(hw_apbh_ch1_debug2)
mxs_reg_32(hw_apbh_ch2_curcmdar)
mxs_reg_32(hw_apbh_ch2_nxtcmdar)
mxs_reg_32(hw_apbh_ch2_cmd)
mxs_reg_32(hw_apbh_ch2_bar)
mxs_reg_32(hw_apbh_ch2_sema)
mxs_reg_32(hw_apbh_ch2_debug1)
mxs_reg_32(hw_apbh_ch2_debug2)
mxs_reg_32(hw_apbh_ch3_curcmdar)
mxs_reg_32(hw_apbh_ch3_nxtcmdar)
mxs_reg_32(hw_apbh_ch3_cmd)
mxs_reg_32(hw_apbh_ch3_bar)
mxs_reg_32(hw_apbh_ch3_sema)
mxs_reg_32(hw_apbh_ch3_debug1)
mxs_reg_32(hw_apbh_ch3_debug2)
mxs_reg_32(hw_apbh_ch4_curcmdar)
mxs_reg_32(hw_apbh_ch4_nxtcmdar)
mxs_reg_32(hw_apbh_ch4_cmd)
mxs_reg_32(hw_apbh_ch4_bar)
mxs_reg_32(hw_apbh_ch4_sema)
mxs_reg_32(hw_apbh_ch4_debug1)
mxs_reg_32(hw_apbh_ch4_debug2)
mxs_reg_32(hw_apbh_ch5_curcmdar)
mxs_reg_32(hw_apbh_ch5_nxtcmdar)
mxs_reg_32(hw_apbh_ch5_cmd)
mxs_reg_32(hw_apbh_ch5_bar)
mxs_reg_32(hw_apbh_ch5_sema)
mxs_reg_32(hw_apbh_ch5_debug1)
mxs_reg_32(hw_apbh_ch5_debug2)
mxs_reg_32(hw_apbh_ch6_curcmdar)
mxs_reg_32(hw_apbh_ch6_nxtcmdar)
mxs_reg_32(hw_apbh_ch6_cmd)
mxs_reg_32(hw_apbh_ch6_bar)
mxs_reg_32(hw_apbh_ch6_sema)
mxs_reg_32(hw_apbh_ch6_debug1)
mxs_reg_32(hw_apbh_ch6_debug2)
mxs_reg_32(hw_apbh_ch7_curcmdar)
mxs_reg_32(hw_apbh_ch7_nxtcmdar)
mxs_reg_32(hw_apbh_ch7_cmd)
mxs_reg_32(hw_apbh_ch7_bar)
mxs_reg_32(hw_apbh_ch7_sema)
mxs_reg_32(hw_apbh_ch7_debug1)
mxs_reg_32(hw_apbh_ch7_debug2)
};
};
mxs_reg_32(hw_apbh_version)
};
#elif defined(CONFIG_MX28)
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
......@@ -169,10 +250,26 @@ struct mxs_apbh_regs {
};
#endif
#endif
#define APBH_CTRL0_SFTRST (1 << 31)
#define APBH_CTRL0_CLKGATE (1 << 30)
#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
#define APBH_CTRL0_APB_BURST_EN (1 << 28)
#if defined(CONFIG_MX23)
#define APBH_CTRL0_RSVD0_MASK (0xf << 24)
#define APBH_CTRL0_RSVD0_OFFSET 24
#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
#elif defined(CONFIG_MX28)
#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
#define APBH_CTRL0_RSVD0_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
......@@ -191,6 +288,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#endif
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
......@@ -260,6 +358,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
#if defined(CONFIG_MX28)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
......@@ -292,7 +391,26 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
#if defined(CONFIG_MX23)
#define APBH_DEVSEL_CH7_MASK (0xf << 28)
#define APBH_DEVSEL_CH7_OFFSET 28
#define APBH_DEVSEL_CH6_MASK (0xf << 24)
#define APBH_DEVSEL_CH6_OFFSET 24
#define APBH_DEVSEL_CH5_MASK (0xf << 20)
#define APBH_DEVSEL_CH5_OFFSET 20
#define APBH_DEVSEL_CH4_MASK (0xf << 16)
#define APBH_DEVSEL_CH4_OFFSET 16
#define APBH_DEVSEL_CH3_MASK (0xf << 12)
#define APBH_DEVSEL_CH3_OFFSET 12
#define APBH_DEVSEL_CH2_MASK (0xf << 8)
#define APBH_DEVSEL_CH2_OFFSET 8
#define APBH_DEVSEL_CH1_MASK (0xf << 4)
#define APBH_DEVSEL_CH1_OFFSET 4
#define APBH_DEVSEL_CH0_MASK (0xf << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#elif defined(CONFIG_MX28)
#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
#define APBH_DEVSEL_CH15_OFFSET 30
#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
......@@ -325,7 +443,9 @@ struct mxs_apbh_regs {
#define APBH_DEVSEL_CH1_OFFSET 2
#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#endif
#if defined(CONFIG_MX28)
#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
......@@ -377,6 +497,7 @@ struct mxs_apbh_regs {
#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
#endif
#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
......
arch/arm/include/asm/arch-mxs/regs-base.h
+ 51
− 5
View file @ e5f5c4a9
/*
* Freescale i.MX28 Peripheral Base Addresses
* Freescale i.MX23/i.MX28 Peripheral Base Addresses
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
......@@ -25,12 +25,55 @@
*
*/
#ifndef __MX28_REGS_BASE_H__
#define __MX28_REGS_BASE_H__
#ifndef __MXS_REGS_BASE_H__
#define __MXS_REGS_BASE_H__
/*
* Register base address
* Register base addresses for i.MX23
*/
#if defined(CONFIG_MX23)
#define MXS_ICOLL_BASE 0x80000000
#define MXS_APBH_BASE 0x80004000
#define MXS_ECC8_BASE 0x80008000
#define MXS_BCH_BASE 0x8000A000
#define MXS_GPMI_BASE 0x8000C000
#define MXS_SSP0_BASE 0x80010000
#define MXS_SSP1_BASE 0x80034000
#define MXS_ETM_BASE 0x80014000
#define MXS_PINCTRL_BASE 0x80018000
#define MXS_DIGCTL_BASE 0x8001C000
#define MXS_EMI_BASE 0x80020000
#define MXS_APBX_BASE 0x80024000
#define MXS_DCP_BASE 0x80028000
#define MXS_PXP_BASE 0x8002A000
#define MXS_OCOTP_BASE 0x8002C000
#define MXS_AXI_BASE 0x8002E000
#define MXS_LCDIF_BASE 0x80030000
#define MXS_SSP1_BASE 0x80034000
#define MXS_TVENC_BASE 0x80038000
#define MXS_CLKCTRL_BASE 0x80040000
#define MXS_SAIF0_BASE 0x80042000
#define MXS_POWER_BASE 0x80044000
#define MXS_SAIF1_BASE 0x80046000
#define MXS_AUDIOOUT_BASE 0x80048000
#define MXS_AUDIOIN_BASE 0x8004C000
#define MXS_LRADC_BASE 0x80050000
#define MXS_SPDIF_BASE 0x80054000
#define MXS_I2C0_BASE 0x80058000
#define MXS_RTC_BASE 0x8005C000
#define MXS_PWM_BASE 0x80064000
#define MXS_TIMROT_BASE 0x80068000
#define MXS_UARTAPP0_BASE 0x8006C000
#define MXS_UARTAPP1_BASE 0x8006E000
#define MXS_UARTDBG_BASE 0x80070000
#define MXS_USBPHY0_BASE 0x8007C000
#define MXS_USBCTRL0_BASE 0x80080000
#define MXS_DRAM_BASE 0x800E0000
/*
* Register base addresses for i.MX28
*/
#elif defined(CONFIG_MX28)
#define MXS_ICOL_BASE 0x80000000
#define MXS_HSADC_BASE 0x80002000
#define MXS_APBH_BASE 0x80004000
......@@ -84,5 +127,8 @@
#define MXS_DRAM_BASE 0x800E0000
#define MXS_ENET0_BASE 0x800F0000
#define MXS_ENET1_BASE 0x800F4000
#else
#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
#endif
#endif /* __MX28_REGS_BASE_H__ */
#endif /* __MXS_REGS_BASE_H__ */
arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h 0 → 100644
+ 221
− 0
View file @ e5f5c4a9
/*
* Freescale i.MX23 CLKCTRL Register Definitions
*
* Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX23_REGS_CLKCTRL_H__
#define __MX23_REGS_CLKCTRL_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */
mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */
mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */
mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */
mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */
uint32_t reserved1[4];
mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */
mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */
mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */
mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */
mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */
mxs_reg_32(hw_clkctrl_reset) /* 0x120 */
mxs_reg_32(hw_clkctrl_status) /* 0x130 */
mxs_reg_32(hw_clkctrl_version) /* 0x140 */
};
#endif
#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
#define CLKCTRL_PLL0CTRL0_POWER (1 << 16)
#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
#define CLKCTRL_HBUS_BUSY (1 << 29)
#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28)
#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27)
#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20)
#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
#define CLKCTRL_HBUS_DIV_MASK 0x1f
#define CLKCTRL_HBUS_DIV_OFFSET 0
#define CLKCTRL_XBUS_BUSY (1 << 31)
#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_XBUS_DIV_MASK 0x3ff
#define CLKCTRL_XBUS_DIV_OFFSET 0
#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30)
#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28)
#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27)
#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
#define CLKCTRL_PIX_CLKGATE (1 << 31)
#define CLKCTRL_PIX_BUSY (1 << 29)
#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12)
#define CLKCTRL_PIX_DIV_MASK 0xfff
#define CLKCTRL_PIX_DIV_OFFSET 0
#define CLKCTRL_SSP_CLKGATE (1 << 31)
#define CLKCTRL_SSP_BUSY (1 << 29)
#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
#define CLKCTRL_SSP_DIV_MASK 0x1ff
#define CLKCTRL_SSP_DIV_OFFSET 0
#define CLKCTRL_GPMI_CLKGATE (1 << 31)
#define CLKCTRL_GPMI_BUSY (1 << 29)
#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_GPMI_DIV_MASK 0x3ff
#define CLKCTRL_GPMI_DIV_OFFSET 0
#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
#define CLKCTRL_EMI_CLKGATE (1 << 31)
#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
#define CLKCTRL_IR_CLKGATE (1 << 31)
#define CLKCTRL_IR_AUTO_DIV (1 << 29)
#define CLKCTRL_IR_IR_BUSY (1 << 28)
#define CLKCTRL_IR_IROV_BUSY (1 << 27)
#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16)
#define CLKCTRL_IR_IROV_DIV_OFFSET 16
#define CLKCTRL_IR_IR_DIV_MASK 0x3ff
#define CLKCTRL_IR_IR_DIV_OFFSET 0
#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
#define CLKCTRL_SAIF0_BUSY (1 << 29)
#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
#define CLKCTRL_SAIF0_DIV_MASK 0xffff
#define CLKCTRL_SAIF0_DIV_OFFSET 0
#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31)
#define CLKCTRL_TV_CLK_TV_GATE (1 << 30)
#define CLKCTRL_ETM_CLKGATE (1 << 31)
#define CLKCTRL_ETM_BUSY (1 << 29)
#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6)
#define CLKCTRL_ETM_DIV_MASK 0x3f
#define CLKCTRL_ETM_DIV_OFFSET 0
#define CLKCTRL_FRAC_CLKGATE (1 << 7)
#define CLKCTRL_FRAC_STABLE (1 << 6)
#define CLKCTRL_FRAC_FRAC_MASK 0x3f
#define CLKCTRL_FRAC_FRAC_OFFSET 0
#define CLKCTRL_FRAC0_CPU 0
#define CLKCTRL_FRAC0_EMI 1
#define CLKCTRL_FRAC0_PIX 2
#define CLKCTRL_FRAC0_IO0 3
#define CLKCTRL_FRAC1_VID 3
#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5)
#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3)
#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1)
#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0)
#define CLKCTRL_RESET_CHIP (1 << 1)
#define CLKCTRL_RESET_DIG (1 << 0)
#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
#define CLKCTRL_VERSION_MAJOR_OFFSET 24
#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
#define CLKCTRL_VERSION_MINOR_OFFSET 16
#define CLKCTRL_VERSION_STEP_MASK 0xffff
#define CLKCTRL_VERSION_STEP_OFFSET 0
#endif /* __MX23_REGS_CLKCTRL_H__ */
arch/arm/include/asm/arch-mxs/regs-digctl.h
+ 1
− 0
View file @ e5f5c4a9
......@@ -154,6 +154,7 @@ struct mxs_digctl_regs {
/* Product code identification */
#define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
#endif /* __MX28_REGS_DIGCTL_H__ */
arch/arm/include/asm/arch-mxs/regs-power-mx23.h 0 → 100644
+ 358
− 0
View file @ e5f5c4a9
/*
* Freescale i.MX23 Power Controller Register Definitions
*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX23_REGS_POWER_H__
#define __MX23_REGS_POWER_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
mxs_reg_32(hw_power_ctrl)
mxs_reg_32(hw_power_5vctrl)
mxs_reg_32(hw_power_minpwr)
mxs_reg_32(hw_power_charge)
uint32_t hw_power_vdddctrl;
uint32_t reserved_vddd[3];
uint32_t hw_power_vddactrl;
uint32_t reserved_vdda[3];
uint32_t hw_power_vddioctrl;
uint32_t reserved_vddio[3];
uint32_t hw_power_vddmemctrl;
uint32_t reserved_vddmem[3];
uint32_t hw_power_dcdc4p2;
uint32_t reserved_dcdc4p2[3];
uint32_t hw_power_misc;
uint32_t reserved_misc[3];
uint32_t hw_power_dclimits;
uint32_t reserved_dclimits[3];
mxs_reg_32(hw_power_loopctrl)
uint32_t hw_power_sts;
uint32_t reserved_sts[3];
mxs_reg_32(hw_power_speed)
uint32_t hw_power_battmonitor;
uint32_t reserved_battmonitor[3];
uint32_t reserved1[4];
mxs_reg_32(hw_power_reset)
uint32_t reserved2[4];
mxs_reg_32(hw_power_special)
mxs_reg_32(hw_power_version)
};
#endif
#define POWER_CTRL_CLKGATE (1 << 30)
#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
#define POWER_CTRL_DC_OK_IRQ (1 << 15)
#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28)
#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20)
#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
#define POWER_5VCTRL_DCDC_XFER (1 << 5)
#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13)
#define POWER_MINPWR_PWD_BO (1 << 12)
#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
#define POWER_MINPWR_ENABLE_OSC (1 << 9)
#define POWER_MINPWR_SELECT_OSC (1 << 8)
#define POWER_MINPWR_VBG_OFF (1 << 7)
#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
#define POWER_MINPWR_HALFFETS (1 << 5)
#define POWER_MINPWR_LESSANA_I (1 << 4)
#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
#define POWER_MINPWR_DC_STOPCLK (1 << 2)
#define POWER_MINPWR_EN_DC_PFM (1 << 1)
#define POWER_MINPWR_DC_HALFCLK (1 << 0)
#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21)
#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
#define POWER_CHARGE_USE_EXTERN_R (1 << 17)
#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
#define POWER_VDDDCTRL_ADJTN_OFFSET 28
#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDDCTRL_TRG_MASK 0x1f
#define POWER_VDDDCTRL_TRG_OFFSET 0
#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDACTRL_TRG_MASK 0x1f
#define POWER_VDDACTRL_TRG_OFFSET 0
#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDIOCTRL_TRG_MASK 0x1f
#define POWER_VDDIOCTRL_TRG_OFFSET 0
#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
#define POWER_VDDMEMCTRL_TRG_OFFSET 0
#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
#define POWER_DCDC4P2_HYST_DIR (1 << 21)
#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
#define POWER_DCDC4P2_TRG_OFFSET 16
#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
#define POWER_DCDC4P2_BO_OFFSET 8
#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
#define POWER_MISC_FREQSEL_OFFSET 4
#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
#define POWER_MISC_DELAY_TIMING (1 << 2)
#define POWER_MISC_TEST (1 << 1)
#define POWER_MISC_SEL_PLLCLK (1 << 0)
#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
#define POWER_LOOPCTRL_DC_FF_OFFSET 8
#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
#define POWER_LOOPCTRL_DC_R_OFFSET 4
#define POWER_LOOPCTRL_DC_C_MASK 0x3
#define POWER_LOOPCTRL_DC_C_OFFSET 0
#define POWER_LOOPCTRL_DC_C_MAX 0x0
#define POWER_LOOPCTRL_DC_C_2X 0x1
#define POWER_LOOPCTRL_DC_C_4X 0x2
#define POWER_LOOPCTRL_DC_C_MIN 0x3
#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
#define POWER_STS_PWRUP_SOURCE_OFFSET 24
#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
#define POWER_STS_PSWITCH_MASK (0x3 << 20)
#define POWER_STS_PSWITCH_OFFSET 20
#define POWER_STS_AVALID0_STATUS (1 << 17)
#define POWER_STS_BVALID0_STATUS (1 << 16)
#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
#define POWER_STS_SESSEND0_STATUS (1 << 14)
#define POWER_STS_BATT_BO (1 << 13)
#define POWER_STS_VDD5V_FAULT (1 << 12)
#define POWER_STS_CHRGSTS (1 << 11)
#define POWER_STS_DCDC_4P2_BO (1 << 10)
#define POWER_STS_DC_OK (1 << 9)
#define POWER_STS_VDDIO_BO (1 << 8)
#define POWER_STS_VDDA_BO (1 << 7)
#define POWER_STS_VDDD_BO (1 << 6)
#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
#define POWER_STS_VDD5V_DROOP (1 << 4)
#define POWER_STS_AVALID0 (1 << 3)
#define POWER_STS_BVALID0 (1 << 2)
#define POWER_STS_VBUSVALID0 (1 << 1)
#define POWER_STS_SESSEND0 (1 << 0)
#define POWER_SPEED_STATUS_MASK (0xff << 16)
#define POWER_SPEED_STATUS_OFFSET 16
#define POWER_SPEED_CTRL_MASK 0x3
#define POWER_SPEED_CTRL_OFFSET 0
#define POWER_SPEED_CTRL_SS_OFF 0x0
#define POWER_SPEED_CTRL_SS_ON 0x1
#define POWER_SPEED_CTRL_SS_ENABLE 0x3
#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
#define POWER_RESET_UNLOCK_OFFSET 16
#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
#define POWER_RESET_PWD_OFF (1 << 1)
#define POWER_RESET_PWD (1 << 0)
#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
#define POWER_SPECIAL_TEST_MASK 0xffffffff
#define POWER_SPECIAL_TEST_OFFSET 0
#define POWER_VERSION_MAJOR_MASK (0xff << 24)
#define POWER_VERSION_MAJOR_OFFSET 24
#define POWER_VERSION_MINOR_MASK (0xff << 16)
#define POWER_VERSION_MINOR_OFFSET 16
#define POWER_VERSION_STEP_MASK 0xffff
#define POWER_VERSION_STEP_OFFSET 0
#endif /* __MX23_REGS_POWER_H__ */
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