- Apr 08, 2011
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Cliff Cai authored
The timer register is 32bits, not 16bit, so 0xFFFF won't fill it. Write out -1 to make sure to fill the whole thing. Signed-off-by:
Cliff Cai <cliff.cai@analog.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Simple command to decode/check an LDR image before we try to boot it. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Now that the common bootrom.h sets up defines for us, switch to them rather than our own local set. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
We need the updated LDR bit defines for our LDR utils. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
This define isn't used anywhere anymore, so punt it. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Some parts lack Bank B in L1 data, so have the linker script fall back to Bank A when that happens. This way we can still leverage L1 data. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
When bootstrapping ourselves on the fly at runtime (via "go"), we need to turn off the caches to avoid taking software exceptions. Since caches need CPLBs and CPLBs need exception handlers, but we're about to rewrite the code in memory where those exception handlers live, we need to turn off caches first. This new code also encourages a slight code optimization by storing the MMR bases in dedicated registers so we don't have to fully load up the pointer regs multiple times. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
If the part has no external memory configured, then there will be no os log for us to check, and any attempt to access that memory will trigger hardware errors. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Common code already takes care of setting up these defines when a port hasn't specified them, so punt the duplicate values. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
The recent global data changes (making the size autogenerated) broke the board info handling on Blackfin ports as we were lying and lumping the bd_t size in with the gd_t size. So use the new dedicated bd_t size to setup its own address in memory. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Have CONFIG_ENV_ADDR be based on CONFIG_ENV_OFFSET rather than the other way around so that we can use CONFIG_ENV_OFFSET during build. It also avoids a little address duplication. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use the one coming from the compiler. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Fixes a build error due to new partial linking logic. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Chong Huang authored
Signed-off-by:
Chong Huang <chuang@ucrobotics.com> Signed-off-by:
Haitao Zhang <minipanda@linuxrobot.org> Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Andreas Schallenberg authored
Info about the hardware can be found here: http://www.dilnetpc.com/dnp0086.htm Signed-off-by:
Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de> Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Looks like the filesystem shuffling missed the SDP board. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
This is a revert of 821ad16f as Wolfgang doesn't like the new code. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Unify this convention for all Blackfin boards. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
We don't want/use this value for Blackfin boards, so punt it and have the common code error out when people try to use it. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Only the first run of boards had a ksz switch on it, so if building for a newer silicon rev or SPI is disabled, don't bother checking for the ksz. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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- Apr 05, 2011
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git://git.denx.de/u-boot-mpc85xxWolfgang Denk authored
Conflicts: drivers/usb/host/ehci-pci.c Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Timur Tabi authored
Clean up the macro defintions used to enable DIU (video) support on the MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS, which is newer. Add software cursor support to all three boards. Also document the CONFIG_FSL_DIU_FB in the README. Signed-off-by:
Timur Tabi <timur@freescale.com> Acked-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Jerry Huang authored
We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
Zhao Chenhui <b35336@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Mingkai Hu authored
On some boards the environment may not be located at a fixed address in the MMC/SDHC card. This allows those boards to implement their own means to report what address the environment is located at. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
Zhao Chenhui <b35336@freescale.com> Acked-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Apr 04, 2011
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kyle Moffett authored
The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by:
Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kyle Moffett authored
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies. Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily restructure the computation to use the "do_div()" function to perform 64-bit/32-bit divide operations. On 64-bit this change is basically a no-op, because do_div is implemented as a literal 64-bit divide operation and the instruction scheduling works out almost the same. On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is over 1.1kB of code and thousands of heavily dependent cycles to compute, all of which is linked from libgcc. Another 1.2kB of code comes in for the function __umoddi3. It should be noted that nothing else in U-Boot or the Linux kernel seems to require a full 64-bit divide on my 32-bit PowerPC. Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection. Signed-off-by:
Kyle Moffett <Kyle.D.Moffett@boeing.com> Acked-by:
York Sun <yorksun@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Laurentiu TUDOR authored
We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by:
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Jiang Yutang authored
Signed-off-by:
Jiang Yutang <b14898@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Li Yang authored
Signed-off-by:
Li Yang <leoli@freescale.com>
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bhaskar upadhaya authored
Fix up the device tree property associated with the IEEE 1588 timer source frequency. Currently we only support the IEEE 1588 timer source being the internal eTSEC system clock (for those SoCs with IEEE 1588 support). The eTSEC clock is ccb_clk/2. Signed-off-by:
Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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