Commit 4a0d4350 authored by Sebastian Dröge's avatar Sebastian Dröge
Browse files

volume: Fix unit test failure for the controlled processing functions

Going over integer arithmetic will lead to minimal rounding errors,
leading to +/-1 changes for volume==1.0. Implement the controlled
processing with floating point arithmetic, which was already done
for the C versions anyway.
parent 7c423ba4
......@@ -780,8 +780,6 @@ volume_process_controlled_int8_clamp (GstVolume * self, gpointer bytes,
orc_process_controlled_int8_1ch (data, volume, num_samples);
} else if (channels == 2) {
orc_process_controlled_int8_2ch (data, volume, num_samples);
} else if (channels == 4) {
orc_process_controlled_int8_4ch (data, volume, num_samples);
} else {
for (i = 0; i < num_samples; i++) {
vol = *volume++;
......
......@@ -112,97 +112,69 @@ x2 mulf d1, d1, t2
.dest 4 d1 gint32
.source 8 s1 gdouble
.temp 8 t1
.temp 4 t2
muld t1, s1, 0x41E0000000000000L
convdl t2, t1
mulslq t1, d1, t2
addq t1, t1, 0x0FFFFFFFL
shrsq t1, t1, 31
convql d1, t1
convld t1, d1
muld t1, t1, s1
convdl d1, t1
.function orc_process_controlled_int16_1ch
.dest 2 d1 gint16
.source 8 s1 gdouble
.temp 8 t1
.temp 4 t1
.temp 4 t2
.temp 2 t3
muld t1, s1, 0x40E0000000000000L
convdl t2, t1
convssslw t3, t2
mulswl t2, t3, d1
addl t2, t2, 0x0FFF
shrsl t2, t2, 15
convlw d1, t2
convswl t1, d1
convlf t1, t1
convdf t2, s1
mulf t1, t1, t2
convfl t1, t1
convssslw d1, t1
.function orc_process_controlled_int16_2ch
.dest 4 d1 gint16
.source 8 s1 gdouble
.temp 8 t1
.temp 4 t2
.temp 2 t3
.temp 8 t3
muld t1, s1, 0x40E0000000000000L
convdl t2, t1
convssslw t3, t2
mergewl t2, t3, t3
x2 mulswl t1, t2, d1
x2 addl t1, t1, 0x0FFF
x2 shrsl t1, t1, 15
x2 convlw d1, t1
x2 convswl t1, d1
x2 convlf t1, t1
convdf t2, s1
mergelq t3, t2, t2
x2 mulf t3, t3, t1
x2 convfl t3, t3
x2 convssslw d1, t3
.function orc_process_controlled_int8_1ch
.dest 1 d1 gint8
.source 8 s1 gdouble
.temp 8 t1
.temp 2 t1
.temp 4 t2
.temp 2 t3
.temp 1 t4
muld t1, s1, 0x4060000000000000L
convdl t2, t1
convlw t3, t2
convssswb t4, t3
mulsbw t3, t4, d1
addw t3, t3, 0x0F
shrsw t3, t3, 7
convwb d1, t3
.temp 4 t3
convsbw t1, d1
convswl t2, t1
convlf t2, t2
convdf t3, s1
mulf t2, t2, t3
convfl t2, t2
convlw t1, t2
convssswb d1, t1
.function orc_process_controlled_int8_2ch
.dest 2 d1 gint8
.source 8 s1 gdouble
.temp 8 t1
.temp 4 t2
.temp 2 t3
.temp 1 t4
muld t1, s1, 0x4060000000000000L
convdl t2, t1
convlw t3, t2
convssswb t4, t3
mergebw t3, t4, t4
x2 mulsbw t2, t3, d1
x2 addw t2, t2, 0x0F
x2 shrsw t2, t2, 7
x2 convwb d1, t2
.function orc_process_controlled_int8_4ch
.dest 4 d1 gint8
.source 8 s1 gdouble
.temp 8 t1
.temp 4 t2
.temp 2 t3
.temp 1 t4
muld t1, s1, 0x4060000000000000L
convdl t2, t1
convlw t3, t2
convssswb t4, t3
mergebw t3, t4, t4
mergewl t2, t3, t3
x4 mulsbw t1, t2, d1
x4 addw t1, t1, 0x0F
x4 shrsw t1, t1, 7
x4 convwb d1, t1
.temp 4 t1
.temp 8 t2
.temp 8 t3
x2 convsbw t1, d1
x2 convswl t2, t1
x2 convlf t2, t2
convdf t1, s1
mergelq t3, t1, t1
x2 mulf t2, t2, t3
x2 convfl t2, t2
x2 convlw t1, t2
x2 convssswb d1, t1
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