• Madalin Bucur's avatar
    dt-bindings: net: FMan erratum A050385 · 26d5bb9e
    Madalin Bucur authored
    FMAN DMA read or writes under heavy traffic load may cause FMAN
    internal resource leak; thus stopping further packet processing.
    The FMAN internal queue can overflow when FMAN splits single
    read or write transactions into multiple smaller transactions
    such that more than 17 AXI transactions are in flight from FMAN
    to interconnect. When the FMAN internal queue overflows, it can
    stall further packet processing. The issue can occur with any one
    of the following three conditions:
      1. FMAN AXI transaction crosses 4K address boundary (Errata
      2. FMAN DMA address for an AXI transaction is not 16 byte
         aligned, i.e. the last 4 bits of an address are non-zero
      3. Scatter Gather (SG) frames have more than one SG buffer in
         the SG list and any one of the buffers, except the last
         buffer in the SG list has data size that is not a multiple
         of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
    With any one of the above three conditions present, there is
    likelihood of stalled FMAN packet processing, especially under
    stress with multiple ports injecting line-rate traffic.
    To avoid situations that stall FMAN packet processing, all of the
    above three conditions must be avoided; therefore, configure the
    system with the following rules:
      1. Frame buffers must not span a 4KB address boundary, unless
         the frame start address is 256 byte aligned
      2. All FMAN DMA start addresses (for example, BMAN buffer
         address, FD[address] + FD[offset]) are 16B aligned
      3. SG table and buffer addresses are 16B aligned and the size
         of SG buffers are multiple of 16 bytes, except for the last
         SG buffer that can be of any size.
    Additional workaround notes:
    - Address alignment of 64 bytes is recommended for maximally
    efficient system bus transactions (although 16 byte alignment is
    sufficient to avoid the stall condition)
    - To support frame sizes that are larger than 4K bytes, there are
    two options:
      1. Large single buffer frames that span a 4KB page boundary can
         be converted into SG frames to avoid transaction splits at
         the 4KB boundary,
      2. Align the large single buffer to 256B address boundaries,
         ensure that the frame address plus offset is 256B aligned.
    - If software generated SG frames have buffers that are unaligned
    and with random non-multiple of 16 byte lengths, before
    transmitting such frames via FMAN, frames will need to be copied
    into a new single buffer or multiple buffer SG frame that is
    compliant with the three rules listed above.
    Signed-off-by: default avatarMadalin Bucur <madalin.bucur@nxp.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
fsl-fman.txt 16 KB