• Will Deacon's avatar
    arm64: entry: Place an SB sequence following an ERET instruction · 679db708
    Will Deacon authored
    
    
    Some CPUs can speculate past an ERET instruction and potentially perform
    speculative accesses to memory before processing the exception return.
    Since the register state is often controlled by a lower privilege level
    at the point of an ERET, this could potentially be used as part of a
    side-channel attack.
    
    This patch emits an SB sequence after each ERET so that speculation is
    held up on exception return.
    
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    679db708