Commit 3883cbb6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'soc-for-linus' of git://

Pull ARM SoC specific changes from Arnd Bergmann:
 "These changes are all to SoC-specific code, a total of 33 branches on
  17 platforms were pulled into this.  Like last time, Renesas sh-mobile
  is now the platform with the most changes, followed by OMAP and

  Two new platforms, TI Keystone and Rockchips RK3xxx are added in this
  branch, both containing almost no platform specific code at all, since
  they are using generic subsystem interfaces for clocks, pinctrl,
  interrupts etc.  The device drivers are getting merged through the
  respective subsystem maintainer trees.

  One more SoC (u300) is now multiplatform capable and several others
  (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving
  towards that goal with this series but need more work.

  Also noteworthy is the work on PCI here, which is traditionally part
  of the SoC specific code.  With the changes done by Thomas Petazzoni,
  we can now more easily have PCI host controller drivers as loadable
  modules and keep them separate from the platform code in
  drivers/pci/host.  This has already led to the discovery that three
  platforms (exynos, spear and imx) are actually using an identical PCIe
  host controller and will be able to share a driver once support for
  spear and imx is added."

* tag 'soc-for-linus' of git:// (480 commits)
  ARM: integrator: let pciv3 use mem/premem from device tree
  ARM: integrator: set local side PCI addresses right
  ARM: dts: Add pcie controller node for exynos5440-ssdk5440
  ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
  ARM: EXYNOS: Enable PCIe support for Exynos5440
  pci: Add PCIe driver for Samsung Exynos
  ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data
  ARM: keystone: Move CPU bringup code to dedicated asm file
  ARM: multiplatform: always pick one CPU type
  ARM: imx: select syscon for IMX6SL
  ARM: keystone: select ARM_ERRATA_798181 only for SMP
  ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1
  ARM: OMAP2+: AM43x: resolve SMP related build error
  dmaengine: edma: enable build for AM33XX
  ARM: edma: Add EDMA crossbar event mux support
  ARM: edma: Add DT and runtime PM support to the private EDMA API
  dmaengine: edma: Add TI EDMA device tree binding
  arm: add basic support for Rockchip RK3066a boards
  arm: add debug uarts for rockchip rk29xx and rk3xxx series
  arm: Add basic clocks for Rockchip rk3066a SoCs
parents d2033f2c 1eb92b24
......@@ -17,6 +17,10 @@ SunXi family
+ User Manual
- Allwinner A10s (sun5i)
+ Datasheet
- Allwinner A13 (sun5i)
+ Datasheet
ARM CCI cache coherent interconnect binding description
ARM multi-cluster systems maintain intra-cluster coherency through a
cache coherent interconnect (CCI) that is capable of monitoring bus
transactions and manage coherency, TLB invalidations and memory barriers.
It allows snooping and distributed virtual memory message broadcast across
clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
Bindings for the CCI node follow the ePAPR standard, available from:
with the addition of the bindings described in this document which are
specific to ARM.
* CCI interconnect node
Description: Describes a CCI cache coherent Interconnect component
Node name must be "cci".
Node's parent must be the root node /, and the address space visible
through the CCI interconnect is the same as the one seen from the
root node (ie from CPUs perspective as per DT standard).
Every CCI node has to define the following properties:
- compatible
Usage: required
Value type: <string>
Definition: must be set to
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies base physical
address of CCI control registers common to all
- ranges:
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Follow rules in the ePAPR for
hierarchical bus addressing. CCI interfaces
addresses refer to the parent node addressing
scheme to declare their register bases.
CCI interconnect node can define the following child nodes:
- CCI control interface nodes
Node name must be "slave-if".
Parent node must be CCI interconnect node.
A CCI control interface node must contain the following
- compatible
Usage: required
Value type: <string>
Definition: must be set to
- interface-type:
Usage: required
Value type: <string>
Definition: must be set to one of {"ace", "ace-lite"}
depending on the interface type the node
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the
corresponding interface programming
* CCI interconnect bus masters
Description: masters in the device tree connected to a CCI port
(inclusive of CPUs and their cpu nodes).
A CCI interconnect bus master node must contain the following
- cci-control-port:
Usage: required
Value type: <phandle>
Definition: a phandle containing the CCI control interface node
the master is connected to.
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x0>;
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x1>;
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x100>;
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x101>;
dma0: dma@3000000 {
compatible = "arm,pl330", "arm,primecell";
cci-control-port = <&cci_control0>;
reg = <0x0 0x3000000 0x0 0x1000>;
interrupts = <10>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x6000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
This CCI node corresponds to a CCI component whose control registers sits
at address 0x000000002c090000.
CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
TI Keystone Platforms Device Tree Bindings
Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the
following properties.
Required properties:
- compatible: All TI specific devices present in Keystone SOC should be in
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
type UART should use the specified compatible for those devices.
ARM Dual Cluster System Configuration Block
The Dual Cluster System Configuration Block (DCSCB) provides basic
functionality for controlling clocks, resets and configuration pins in
the Dual Cluster System implemented by the Real-Time System Model (RTSM).
Required properties:
- compatible : should be "arm,rtsm,dcscb"
- reg : physical base address and the size of the registers window
dcscb@60000000 {
compatible = "arm,rtsm,dcscb";
reg = <0x60000000 0x1000>;
ST-Ericsson U300 Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs
or board power regulator supplies.
Required root node property:
Required node: syscon
This contains the system controller.
- compatible: must be "stericsson,u300-syscon".
- reg: the base address and size of the system controller.
Boards with the U300 SoC include:
S365 "Small Board U365":
Required node: s365
This contains the board-specific information.
- compatible: must be "stericsson,s365".
- vana15-supply: the regulator supplying the 1.5V to drive the
- syscon: a pointer to the syscon node so we can acccess the
syscon registers to set the board as self-powered.
/ {
model = "ST-Ericsson U300";
compatible = "stericsson,u300";
#address-cells = <1>;
#size-cells = <1>;
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
syscon = <&syscon>;
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon";
reg = <0xc0011000 0x1000>;
......@@ -184,6 +184,19 @@ clocks and IDs.
cko2 170
srtc_gate 171
pata_gate 172
sata_gate 173
spdif_xtal_sel 174
spdif0_sel 175
spdif1_sel 176
spdif0_pred 177
spdif0_podf 178
spdif1_pred 179
spdif1_podf 180
spdif0_com_sel 181
spdif1_com_sel 182
spdif0_gate 183
spdif1_gate 184
spdif_ipg_gate 185
Examples (for mx53):
......@@ -208,6 +208,7 @@ clocks and IDs.
pll4_post_div 193
pll5_post_div 194
pll5_video_div 195
eim_slow 196
* Clock bindings for Freescale i.MX6 SoloLite
Required properties:
- compatible: Should be "fsl,imx6sl-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h
for the full list of i.MX6 SoloLite clock IDs.
Clock bindings for ST-Ericsson U300 System Controller Clocks
Bindings for the gated system controller clocks:
Required properties:
- compatible: must be "stericsson,u300-syscon-clk"
- #clock-cells: must be <0>
- clock-type: specifies the type of clock:
0 = slow clock
1 = fast clock
2 = rest/remaining clock
- clock-id: specifies the clock in the type range
Optional properties:
- clocks: parent clock(s)
The available clocks per type are as follows:
Type: ID: Clock:
0 0 Slow peripheral bridge clock
0 1 UART0 clock
0 4 GPIO clock
0 6 RTC clock
0 7 Application timer clock
0 8 Access timer clock
1 0 Fast peripheral bridge clock
1 1 I2C bus 0 clock
1 2 I2C bus 1 clock
1 5 MMC interface peripheral (silicon) clock
1 6 SPI clock
2 3 CPU clock
2 4 DMA controller clock
2 5 External Memory Interface (EMIF) clock
2 6 NAND flask interface clock
2 8 XGAM graphics engine clock
2 9 Shared External Memory Interface (SEMI) clock
2 10 AHB Subsystem Bridge clock
2 12 Interrupt controller clock
gpio_clk: gpio_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <4>;
clocks = <&slow_clk>;
gpio: gpio@c0016000 {
compatible = "stericsson,gpio-coh901";
clocks = <&gpio_clk>;
Bindings for the MMC/SD card clock:
Required properties:
- compatible: must be "stericsson,u300-syscon-mclk"
- #clock-cells: must be <0>
Optional properties:
- clocks: parent clock(s)
mmc_mclk: mmc_mclk {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-mclk";
clocks = <&mmc_pclk>;
mmcsd: mmcsd@c0001000 {
compatible = "arm,pl18x", "arm,primecell";
clocks = <&mmc_pclk>, <&mmc_mclk>;
clock-names = "apb_pclk", "mclk";
* Clock bindings for Freescale Vybrid VF610 SOC
Required properties:
- compatible: Should be "fsl,vf610-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
for the full list of VF610 clock IDs.
clks: ccm@4006b000 {
compatible = "fsl,vf610-ccm";
reg = <0x4006b000 0x1000>;
#clock-cells = <1>;
uart1: serial@40028000 {
compatible = "fsl,vf610-uart";
reg = <0x40028000 0x1000>;
interrupts = <0 62 0x04>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
......@@ -6,50 +6,99 @@ The purpose of this document is to document their usage.
See clock_bindings.txt for more information on the generic clock bindings.
See Chapter 25 of Zynq TRM for more information about Zynq clocks.
== PLLs ==
Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
== Clock Controller ==
The clock controller is a logical abstraction of Zynq's clock tree. It reads
required input clock frequencies from the devicetree and acts as clock provider
for all clock consumers of PS clocks.
Required properties:
- #clock-cells : shall be 0 (only one clock is output from this node)
- compatible : "xlnx,zynq-pll"
- reg : pair of u32 values, which are the address offsets within the SLCR
of the relevant PLL_CTRL register and PLL_CFG register respectively
- clocks : phandle for parent clock. should be the phandle for ps_clk
- #clock-cells : Must be 1
- compatible : "xlnx,ps7-clkc"
- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
(usually 33 MHz oscillators are used for Zynq platforms)
- clock-output-names : List of strings used to name the clock outputs. Shall be
a list of the outputs given below.
Optional properties:
- clock-output-names : name of the output clock
armpll: armpll {
#clock-cells = <0>;
compatible = "xlnx,zynq-pll";
clocks = <&ps_clk>;
reg = <0x100 0x110>;
clock-output-names = "armpll";
== Peripheral clocks ==
- clocks : as described in the clock bindings
- clock-names : as described in the clock bindings
Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
Clock inputs:
The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source.
- swdt_ext_clk
- gem0_emio_clk
- gem1_emio_clk
- mio_clk_XX # with XX = 00..53
Required properties:
- #clock-cells : shall be 1
- compatible : "xlnx,zynq-periph-clock"
- reg : a single u32 value, describing the offset within the SLCR where
the CLK_CTRL register is found for this peripheral
- clocks : phandle for parent clocks. should hold phandles for
the IO_PLL, ARM_PLL, and DDR_PLL in order
- clock-output-names : names of the output clock(s). For peripherals that have
two output clocks (for example, the UART), two clocks
should be listed.
Clock outputs:
0: armpll
1: ddrpll
2: iopll
3: cpu_6or4x
4: cpu_3or2x
5: cpu_2x
6: cpu_1x
7: ddr2x
8: ddr3x
9: dci
10: lqspi
11: smc
12: pcap
13: gem0
14: gem1
15: fclk0
16: fclk1
17: fclk2
18: fclk3
19: can0
20: can1
21: sdio0
22: sdio1
23: uart0
24: uart1
25: spi0
26: spi1
27: dma
28: usb0_aper
29: usb1_aper
30: gem0_aper
31: gem1_aper
32: sdio0_aper
33: sdio1_aper
34: spi0_aper
35: spi1_aper
36: can0_aper
37: can1_aper
38: i2c0_aper
39: i2c1_aper
40: uart0_aper
41: uart1_aper
42: gpio_aper
43: lqspi_aper
44: smc_aper
45: swdt
46: dbg_trc
47: dbg_apb
uart_clk: uart_clk {
clkc: clkc {
#clock-cells = <1>;
compatible = "xlnx,zynq-periph-clock";
clocks = <&iopll &armpll &ddrpll>;
reg = <0x154>;
clock-output-names = "uart0_ref_clk",
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
"gem1_aper", "sdio0_aper", "sdio1_aper",
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
"dbg_trc", "dbg_apb";
# optional props
clocks = <&clkc 16>, <&clk_foo>;
clock-names = "gem1_emio_clk", "can_mio_clk_23";
ST-Ericsson COH 901 318 DMA Controller
This is a DMA controller which has begun as a fork of the
ARM PL08x PrimeCell VHDL code.
Required properties:
- compatible: should be "stericsson,coh901318"
- reg: register locations and length
- interrupts: the single DMA IRQ
- #dma-cells: must be set to <1>, as the channels on the
COH 901 318 are simple and identified by a single number
- dma-channels: the number of DMA channels handled
dmac: dma-controller@c00020000 {
compatible = "stericsson,coh901318";
reg = <0xc0020000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <40>;
Consumers example:
uart0: serial@c0013000 {
compatible = "...";
dmas = <&dmac 17 &dmac 18>;
dma-names = "tx", "rx";
Required properties:
- compatible : "ti,edma3"
- ti,edma-regions: Number of regions
- ti,edma-slots: Number of slots
- #dma-cells: Should be set to <1>
Clients should use a single channel number per DMA request.
- dma-channels: Specify total DMA channels per CC
- reg: Memory map for accessing module
- interrupt-parent: Interrupt controller the interrupt is routed through
- interrupts: Exactly 3 interrupts need to be specified in the order:
1. Transfer completion interrupt.
2. Memory protection interrupt.
3. Error interrupt.
Optional properties:
- ti,hwmods: Name of the hwmods associated to the EDMA
- ti,edma-xbar-event-map: Crossbar event to channel map
edma: edma@49000000 {
reg = <0x49000000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <12 13 14>;
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
#dma-cells = <1>;
dma-channels = <64>;
ti,edma-regions = <4>;
ti,edma-slots = <256>;
ti,edma-xbar-event-map = <1 12
2 13>;
Cirrus Logic CLPS711X GPIO controller
Required properties:
- compatible: Should be "cirrus,clps711x-gpio"
- reg: Physical base GPIO controller registers location and length.
There should be two registers, first is DATA register, the second