Commit 527630fb authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A handful of clk driver fixes.

  Mostly they're around the i.MX drivers fixing the parents of a few
  clks and making KASAN happy with how the message passing code works.

  Besides that we have a TI driver fix for the RTC parent and a fix for
  the basic gate type registration functions introduced this release
  where they didn't actually pass the arguments in the right places to
  the multiplexer function down below"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: imx: Align imx sc clock parent msg structs to 4
  clk: imx: Align imx sc clock msg structs to 4
  clk: Pass correct arguments to __clk_hw_register_gate()
  clk: ti: am43xx: Fix clock parent for RTC clock
  clk: imx8mp: Correct the enet_qos parent clock
  clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parent
parents 7bf8df68 8400ab88
...@@ -560,7 +560,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) ...@@ -560,7 +560,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00); hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80); hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00); hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_apb_sels, ccm_base + 0x8b80); hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00); hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80); hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00); hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
...@@ -686,7 +686,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) ...@@ -686,7 +686,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0); hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0); hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0); hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "enet_axi", ccm_base + 0x43b0, 0); hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0); hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0); hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0);
hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0); hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0);
......
...@@ -43,12 +43,12 @@ struct imx_sc_msg_req_set_clock_rate { ...@@ -43,12 +43,12 @@ struct imx_sc_msg_req_set_clock_rate {
__le32 rate; __le32 rate;
__le16 resource; __le16 resource;
u8 clk; u8 clk;
} __packed; } __packed __aligned(4);
struct req_get_clock_rate { struct req_get_clock_rate {
__le16 resource; __le16 resource;
u8 clk; u8 clk;
} __packed; } __packed __aligned(4);
struct resp_get_clock_rate { struct resp_get_clock_rate {
__le32 rate; __le32 rate;
...@@ -84,7 +84,7 @@ struct imx_sc_msg_get_clock_parent { ...@@ -84,7 +84,7 @@ struct imx_sc_msg_get_clock_parent {
struct req_get_clock_parent { struct req_get_clock_parent {
__le16 resource; __le16 resource;
u8 clk; u8 clk;
} __packed req; } __packed __aligned(4) req;
struct resp_get_clock_parent { struct resp_get_clock_parent {
u8 parent; u8 parent;
} resp; } resp;
...@@ -121,7 +121,7 @@ struct imx_sc_msg_req_clock_enable { ...@@ -121,7 +121,7 @@ struct imx_sc_msg_req_clock_enable {
u8 clk; u8 clk;
u8 enable; u8 enable;
u8 autog; u8 autog;
} __packed; } __packed __aligned(4);
static inline struct clk_scu *to_clk_scu(struct clk_hw *hw) static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
{ {
......
...@@ -78,7 +78,7 @@ static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst ...@@ -78,7 +78,7 @@ static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst
}; };
static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = { static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
{ AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
{ 0 }, { 0 },
}; };
......
...@@ -522,9 +522,9 @@ struct clk *clk_register_gate(struct device *dev, const char *name, ...@@ -522,9 +522,9 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
* @clk_gate_flags: gate-specific flags for this clock * @clk_gate_flags: gate-specific flags for this clock
* @lock: shared register lock for this clock * @lock: shared register lock for this clock
*/ */
#define clk_hw_register_gate_parent_hw(dev, name, parent_name, flags, reg, \ #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
bit_idx, clk_gate_flags, lock) \ bit_idx, clk_gate_flags, lock) \
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
NULL, (flags), (reg), (bit_idx), \ NULL, (flags), (reg), (bit_idx), \
(clk_gate_flags), (lock)) (clk_gate_flags), (lock))
/** /**
...@@ -539,10 +539,10 @@ struct clk *clk_register_gate(struct device *dev, const char *name, ...@@ -539,10 +539,10 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
* @clk_gate_flags: gate-specific flags for this clock * @clk_gate_flags: gate-specific flags for this clock
* @lock: shared register lock for this clock * @lock: shared register lock for this clock
*/ */
#define clk_hw_register_gate_parent_data(dev, name, parent_name, flags, reg, \ #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
bit_idx, clk_gate_flags, lock) \ bit_idx, clk_gate_flags, lock) \
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
NULL, (flags), (reg), (bit_idx), \ (flags), (reg), (bit_idx), \
(clk_gate_flags), (lock)) (clk_gate_flags), (lock))
void clk_unregister_gate(struct clk *clk); void clk_unregister_gate(struct clk *clk);
void clk_hw_unregister_gate(struct clk_hw *hw); void clk_hw_unregister_gate(struct clk_hw *hw);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment