Commit d2283cdc authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'irq-urgent-2020-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
 "A set of fixes for interrupt chip drivers:

   - Revert the platform driver conversion of interrupt chip drivers as
     it turned out to create more problems than it solves.

   - Fix a trivial typo in the new module helpers which made probing
     reliably fail.

   - Small fixes in the STM32 and MIPS Ingenic drivers

   - The TI firmware rework which had badly managed dependencies and had
     to wait post rc1"

* tag 'irq-urgent-2020-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/ingenic: Leave parent IRQ unmasked on suspend
  irqchip/stm32-exti: Avoid losing interrupts due to clearing pending bits by mistake
  irqchip: Revert modular support for drivers using IRQCHIP_PLATFORM_DRIVER helperse
  irqchip: Fix probing deferal when using IRQCHIP_PLATFORM_DRIVER helpers
  arm64: dts: k3-am65: Update the RM resource types
  arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings
  arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings
  irqchip/ti-sci-inta: Add support for INTA directly connecting to GIC
  irqchip/ti-sci-inta: Do not store TISCI device id in platform device id field
  dt-bindings: irqchip: Convert ti, sci-inta bindings to yaml
  dt-bindings: irqchip: ti, sci-inta: Update docs to support different parent.
  irqchip/ti-sci-intr: Add support for INTR being a parent to INTR
  dt-bindings: irqchip: Convert ti, sci-intr bindings to yaml
  dt-bindings: irqchip: ti, sci-intr: Update bindings to drop the usage of gic as parent
  firmware: ti_sci: Add support for getting resource with subtype
  firmware: ti_sci: Drop unused structure ti_sci_rm_type_map
  firmware: ti_sci: Drop the device id to resource type translation
parents 0063a82d ceb2465c
Texas Instruments K3 Interrupt Aggregator
=========================================
The Interrupt Aggregator (INTA) provides a centralized machine
which handles the termination of system events to that they can
be coherently processed by the host(s) in the system. A maximum
of 64 events can be mapped to a single interrupt.
Interrupt Aggregator
+-----------------------------------------+
| Intmap VINT |
| +--------------+ +------------+ |
m ------>| | vint | bit | | 0 |.....|63| vint0 |
. | +--------------+ +------------+ | +------+
. | . . | | HOST |
Globalevents ------>| . . |------>| IRQ |
. | . . | | CTRL |
. | . . | +------+
n ------>| +--------------+ +------------+ |
| | vint | bit | | 0 |.....|63| vintx |
| +--------------+ +------------+ |
| |
+-----------------------------------------+
Configuration of these Intmap registers that maps global events to vint is done
by a system controller (like the Device Memory and Security Controller on K3
AM654 SoC). Driver should request the system controller to get the range
of global events and vints assigned to the requesting host. Management
of these requested resources should be handled by driver and requests
system controller to map specific global event to vint, bit pair.
Communication between the host processor running an OS and the system
controller happens through a protocol called TI System Control Interface
(TISCI protocol). For more details refer:
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
TISCI Interrupt Aggregator Node:
-------------------------------
- compatible: Must be "ti,sci-inta".
- reg: Should contain registers location and length.
- interrupt-controller: Identifies the node as an interrupt controller
- msi-controller: Identifies the node as an MSI controller.
- interrupt-parent: phandle of irq parent.
- ti,sci: Phandle to TI-SCI compatible System controller node.
- ti,sci-dev-id: TISCI device ID of the Interrupt Aggregator.
- ti,sci-rm-range-vint: Array of TISCI subtype ids representing vints(inta
outputs) range within this INTA, assigned to the
requesting host context.
- ti,sci-rm-range-global-event: Array of TISCI subtype ids representing the
global events range reaching this IA and are assigned
to the requesting host context.
Example:
--------
main_udmass_inta: interrupt-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x0 0x33d00000 0x0 0x100000>;
interrupt-controller;
msi-controller;
interrupt-parent = <&main_navss_intr>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <179>;
ti,sci-rm-range-vint = <0x0>;
ti,sci-rm-range-global-event = <0x1>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 Interrupt Aggregator
maintainers:
- Lokesh Vutla <lokeshvutla@ti.com>
allOf:
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
description: |
The Interrupt Aggregator (INTA) provides a centralized machine
which handles the termination of system events to that they can
be coherently processed by the host(s) in the system. A maximum
of 64 events can be mapped to a single interrupt.
Interrupt Aggregator
+-----------------------------------------+
| Intmap VINT |
| +--------------+ +------------+ |
m ------>| | vint | bit | | 0 |.....|63| vint0 |
. | +--------------+ +------------+ | +------+
. | . . | | HOST |
Globalevents ------>| . . |----->| IRQ |
. | . . | | CTRL |
. | . . | +------+
n ------>| +--------------+ +------------+ |
| | vint | bit | | 0 |.....|63| vintx |
| +--------------+ +------------+ |
| |
+-----------------------------------------+
Configuration of these Intmap registers that maps global events to vint is
done by a system controller (like the Device Memory and Security Controller
on AM654 SoC). Driver should request the system controller to get the range
of global events and vints assigned to the requesting host. Management
of these requested resources should be handled by driver and requests
system controller to map specific global event to vint, bit pair.
Communication between the host processor running an OS and the system
controller happens through a protocol called TI System Control Interface
(TISCI protocol).
properties:
compatible:
const: ti,sci-inta
reg:
maxItems: 1
interrupt-controller: true
msi-controller: true
ti,interrupt-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Interrupt ranges that converts the INTA output hw irq numbers
to parents's input interrupt numbers.
items:
items:
- description: |
"output_irq" specifies the base for inta output irq
- description: |
"parent's input irq" specifies the base for parent irq
- description: |
"limit" specifies the limit for translation
required:
- compatible
- reg
- interrupt-controller
- msi-controller
- ti,sci
- ti,sci-dev-id
- ti,interrupt-ranges
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
main_udmass_inta: msi-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x0 0x33d00000 0x0 0x100000>;
interrupt-controller;
msi-controller;
interrupt-parent = <&main_navss_intr>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <179>;
ti,interrupt-ranges = <0 0 256>;
};
};
Texas Instruments K3 Interrupt Router
=====================================
The Interrupt Router (INTR) module provides a mechanism to mux M
interrupt inputs to N interrupt outputs, where all M inputs are selectable
to be driven per N output. An Interrupt Router can either handle edge triggered
or level triggered interrupts and that is fixed in hardware.
Interrupt Router
+----------------------+
| Inputs Outputs |
+-------+ | +------+ +-----+ |
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
+-------+ | +------+ +-----+ | controller
| . . | +-------+
+-------+ | . . |----->| IRQ |
| INTA |----------->| . . | +-------+
+-------+ | . +-----+ |
| +------+ | N | |
| | irqM | +-----+ |
| +------+ |
| |
+----------------------+
There is one register per output (MUXCNTL_N) that controls the selection.
Configuration of these MUXCNTL_N registers is done by a system controller
(like the Device Memory and Security Controller on K3 AM654 SoC). System
controller will keep track of the used and unused registers within the Router.
Driver should request the system controller to get the range of GIC IRQs
assigned to the requesting hosts. It is the drivers responsibility to keep
track of Host IRQs.
Communication between the host processor running an OS and the system
controller happens through a protocol called TI System Control Interface
(TISCI protocol). For more details refer:
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
TISCI Interrupt Router Node:
----------------------------
Required Properties:
- compatible: Must be "ti,sci-intr".
- ti,intr-trigger-type: Should be one of the following:
1: If intr supports edge triggered interrupts.
4: If intr supports level triggered interrupts.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value should be 2.
First cell should contain the TISCI device ID of source
Second cell should contain the interrupt source offset
within the device.
- ti,sci: Phandle to TI-SCI compatible System controller node.
- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
assigned to this interrupt router. Each subtype id
corresponds to a range of host irqs.
For more details on TISCI IRQ resource management refer:
https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
Example:
--------
The following example demonstrates both interrupt router node and the consumer
node(main gpio) on the AM654 SoC:
main_intr: interrupt-controller0 {
compatible = "ti,sci-intr";
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
ti,sci = <&dmsc>;
ti,sci-dst-id = <56>;
ti,sci-rm-range-girq = <0x1>;
};
main_gpio0: gpio@600000 {
...
interrupt-parent = <&main_intr>;
interrupts = <57 256>, <57 257>, <57 258>,
<57 259>, <57 260>, <57 261>;
...
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 Interrupt Router
maintainers:
- Lokesh Vutla <lokeshvutla@ti.com>
allOf:
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
description: |
The Interrupt Router (INTR) module provides a mechanism to mux M
interrupt inputs to N interrupt outputs, where all M inputs are selectable
to be driven per N output. An Interrupt Router can either handle edge
triggered or level triggered interrupts and that is fixed in hardware.
Interrupt Router
+----------------------+
| Inputs Outputs |
+-------+ | +------+ +-----+ |
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
+-------+ | +------+ +-----+ | controller
| . . | +-------+
+-------+ | . . |----->| IRQ |
| INTA |----------->| . . | +-------+
+-------+ | . +-----+ |
| +------+ | N | |
| | irqM | +-----+ |
| +------+ |
| |
+----------------------+
There is one register per output (MUXCNTL_N) that controls the selection.
Configuration of these MUXCNTL_N registers is done by a system controller
(like the Device Memory and Security Controller on K3 AM654 SoC). System
controller will keep track of the used and unused registers within the Router.
Driver should request the system controller to get the range of GIC IRQs
assigned to the requesting hosts. It is the drivers responsibility to keep
track of Host IRQs.
Communication between the host processor running an OS and the system
controller happens through a protocol called TI System Control Interface
(TISCI protocol).
properties:
compatible:
const: ti,sci-intr
ti,intr-trigger-type:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 4]
description: |
Should be one of the following.
1 = If intr supports edge triggered interrupts.
4 = If intr supports level triggered interrupts.
interrupt-controller: true
'#interrupt-cells':
const: 1
description: |
The 1st cell should contain interrupt router input hw number.
ti,interrupt-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Interrupt ranges that converts the INTR output hw irq numbers
to parents's input interrupt numbers.
items:
items:
- description: |
"output_irq" specifies the base for intr output irq
- description: |
"parent's input irq" specifies the base for parent irq
- description: |
"limit" specifies the limit for translation
required:
- compatible
- ti,intr-trigger-type
- interrupt-controller
- '#interrupt-cells'
- ti,sci
- ti,sci-dev-id
- ti,interrupt-ranges
examples:
- |
main_gpio_intr: interrupt-controller0 {
compatible = "ti,sci-intr";
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <131>;
ti,interrupt-ranges = <0 360 32>;
};
......@@ -17117,8 +17117,8 @@ S: Maintained
F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
F: drivers/clk/keystone/sci-clk.c
......
......@@ -417,10 +417,10 @@ intr_main_gpio: interrupt-controller0 {
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dst-id = <56>;
ti,sci-rm-range-girq = <0x1>;
ti,sci-dev-id = <100>;
ti,interrupt-ranges = <0 392 32>;
};
main_navss {
......@@ -438,10 +438,11 @@ intr_main_navss: interrupt-controller1 {
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dst-id = <56>;
ti,sci-rm-range-girq = <0x0>, <0x2>;
ti,sci-dev-id = <182>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>;
};
inta_main_udmass: interrupt-controller@33d00000 {
......@@ -452,8 +453,7 @@ inta_main_udmass: interrupt-controller@33d00000 {
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <179>;
ti,sci-rm-range-vint = <0x0>;
ti,sci-rm-range-global-event = <0x1>;
ti,interrupt-ranges = <0 0 256>;
};
secure_proxy_main: mailbox@32c00000 {
......@@ -589,7 +589,7 @@ ringacc: ringacc@3c000000 {
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,dma-ring-reset-quirk;
ti,sci = <&dmsc>;
ti,sci-dev-id = <187>;
......@@ -609,11 +609,11 @@ main_udmap: dma-controller@31150000 {
ti,sci-dev-id = <188>;
ti,ringacc = <&ringacc>;
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
<0x2>; /* TX_CHAN */
ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
<0x5>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
<0xd>; /* TX_CHAN */
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
<0xa>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
};
cpts@310d0000 {
......@@ -622,7 +622,7 @@ cpts@310d0000 {
reg-names = "cpts";
clocks = <&main_cpts_mux>;
clock-names = "cpts";
interrupts-extended = <&intr_main_navss 163 0>;
interrupts-extended = <&intr_main_navss 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
......@@ -645,8 +645,7 @@ main_gpio0: main_gpio0@600000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&intr_main_gpio>;
interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
<57 261>;
interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <96>;
......@@ -661,8 +660,7 @@ main_gpio1: main_gpio1@601000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&intr_main_gpio>;
interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
<58 261>;
interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <90>;
......
......@@ -134,7 +134,7 @@ mcu_ringacc: ringacc@2b800000 {
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,dma-ring-reset-quirk;
ti,sci = <&dmsc>;
ti,sci-dev-id = <195>;
......@@ -154,11 +154,11 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-dev-id = <194>;
ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
<0x2>; /* TX_CHAN */
ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
<0x4>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
<0xd>; /* TX_CHAN */
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
<0xa>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
};
};
......
......@@ -74,10 +74,10 @@ intr_wkup_gpio: interrupt-controller2 {
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dst-id = <56>;
ti,sci-rm-range-girq = <0x4>;
ti,sci-dev-id = <156>;
ti,interrupt-ranges = <0 712 16>;
};
wkup_gpio0: wkup_gpio0@42110000 {
......@@ -86,7 +86,7 @@ wkup_gpio0: wkup_gpio0@42110000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&intr_wkup_gpio>;
interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
interrupts = <60>, <61>, <62>, <63>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <56>;
......
......@@ -384,7 +384,7 @@ &pcie1_ep {
};
&mailbox0_cluster0 {
interrupts = <164 0>;
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-tx = <1 0 0>;
......@@ -393,7 +393,7 @@ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
};
&mailbox0_cluster1 {
interrupts = <165 0>;
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-tx = <1 0 0>;
......
......@@ -287,7 +287,7 @@ &wkup_gpio1 {
};
&mailbox0_cluster0 {
interrupts = <214 0>;
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
......@@ -301,7 +301,7 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
};
&mailbox0_cluster1 {
interrupts = <215 0>;
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
......@@ -315,7 +315,7 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
};
&mailbox0_cluster2 {
interrupts = <216 0>;
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
......@@ -329,7 +329,7 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
};
&mailbox0_cluster3 {
interrupts = <217 0>;
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
ti,mbox-rx = <0 0 0>;
......@@ -343,7 +343,7 @@ mbox_c66_1: mbox-c66-1 {
};
&mailbox0_cluster4 {
interrupts = <218 0>;
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
......
......@@ -80,10 +80,10 @@ main_gpio_intr: interrupt-controller0 {
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dst-id = <14>;
ti,sci-rm-range-girq = <0x1>;
ti,sci-dev-id = <131>;
ti,interrupt-ranges = <8 392 56>;
};
main_navss {
......@@ -101,10 +101,12 @@ main_navss_intr: interrupt-controller1 {
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dst-id = <14>;
ti,sci-rm-range-girq = <0>, <2>;
ti,sci-dev-id = <213>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>,
<128 672 64>;
};
main_udmass_inta: interrupt-controller@33d00000 {
......@@ -115,8 +117,7 @@ main_udmass_inta: interrupt-controller@33d00000 {
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <209>;
ti,sci-rm-range-vint = <0xa>;
ti,sci-rm-range-global-event = <0xd>;
ti,interrupt-ranges = <0 0 256>;
};
secure_proxy_main: mailbox@32c00000 {
......@@ -296,7 +297,7 @@ cpts@310d0000 {
reg-names = "cpts";
clocks = <&k3_clks 201 1>;
clock-names = "cpts";
interrupts-extended = <&main_navss_intr 201 0>;
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
......@@ -688,8 +689,8 @@ main_gpio0: gpio@600000 {
gpio-controller;