Commit d92f842b authored by Scott Tsai's avatar Scott Tsai Committed by Paul E. McKenney
Browse files

memory-barriers.txt: Fix typo in pairing example

In the "general barrier pairing with implicit control depdendency"
example, the last write by CPU 1 was meant to change variable x and not
y. The example would be pretty uninteresting if no CPU ever changes x
and the variable was initialized to zero.
Signed-off-by: default avatarScott Tsai <>
Signed-off-by: default avatarPaul E. McKenney <>
parent 0902b1f4
......@@ -947,7 +947,7 @@ Or even:
=============== ===============================
r1 = READ_ONCE(y);
<general barrier>
WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
<implicit control dependency>
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