1. 26 Sep, 2006 7 commits
  2. 30 Jun, 2006 1 commit
  3. 26 Jun, 2006 3 commits
  4. 23 Jun, 2006 1 commit
  5. 31 Mar, 2006 1 commit
    • OGAWA Hirofumi's avatar
      [PATCH] Don't pass boot parameters to argv_init[] · 9b41046c
      OGAWA Hirofumi authored
      
      
      The boot cmdline is parsed in parse_early_param() and
      parse_args(,unknown_bootoption).
      
      And __setup() is used in obsolete_checksetup().
      
      	start_kernel()
      		-> parse_args()
      			-> unknown_bootoption()
      				-> obsolete_checksetup()
      
      If __setup()'s callback (->setup_func()) returns 1 in
      obsolete_checksetup(), obsolete_checksetup() thinks a parameter was
      handled.
      
      If ->setup_func() returns 0, obsolete_checksetup() tries other
      ->setup_func().  If all ->setup_func() that matched a parameter returns 0,
      a parameter is seted to argv_init[].
      
      Then, when runing /sbin/init or init=app, argv_init[] is passed to the app.
      If the app doesn't ignore those arguments, it will warning and exit.
      
      This patch fixes a wrong usage of it, however fixes obvious one only.
      Signed-off-by: default avatarOGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      9b41046c
  6. 25 Mar, 2006 1 commit
    • Vivek Goyal's avatar
      [PATCH] x86_64: timer interrupt lockup due to pending interrupt · da7ed9f9
      Vivek Goyal authored
      
      
      o check_timer() routine fails while second kernel is booting after a crash
        on an opetron box. Problem happens because timer vector (0x31) seems to be
        locked.
      
      o After a system crash, it is not safe to service interrupts any more, hence
        interrupts are disabled. This leads to pending interrupts at LAPIC. LAPIC
        sends these interrupts to the CPU during early boot of second kernel. Other
        pending interrupts are discarded saying unexpected trap but timer interrupt
        is serviced and CPU does not issue an LAPIC EOI because it think this
        interrupt came from i8259 and sends ack to 8259. This leads to vector 0x31
        locking as LAPIC does not clear respective ISR and keeps on waiting for
        EOI.
      
      o This patch issues extra EOI for the pending interrupts who have ISR set.
      
      o Though today only timer seems to be the special case because in early
        boot it thinks interrupts are coming from i8259 and uses
        mask_and_ack_8259A() as ack handler and does not issue LAPIC EOI. But
        probably doing it in generic manner for all vectors makes sense.
      Signed-off-by: default avatarVivek Goyal <vgoyal@in.ibm.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      da7ed9f9
  7. 28 Feb, 2006 1 commit
  8. 26 Feb, 2006 1 commit
  9. 17 Feb, 2006 1 commit
  10. 12 Feb, 2006 1 commit
    • Chris McDermott's avatar
      [PATCH] x86-64: Fix HPET timer on x460 · 33042a9f
      Chris McDermott authored
      
      
      [description from AK]
      
      The IBM Summit 3 chipset doesn't implement the HPET timer replacement
      option.  Since the current Linux code relies on it use a mixed mode with
      both PIT for the interrupt and HPET counters for the time keeping.  That
      was already implemented, but didn't work properly because it was still
      using the last interrupt offset in HPET.  This resulted in x460 not
      booting.  Fix this up by using the free running HPET counter.
      
      Shouldn't affect any other machine because they either use full HPET mode
      or no HPET at all.
      
      TBD needs a similar 32bit fix.
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Cc: Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>
      Cc: Bob Picco <bob.picco@hp.com>
      Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
      Cc: john stultz <johnstul@us.ibm.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      33042a9f
  11. 05 Feb, 2006 4 commits
  12. 16 Jan, 2006 1 commit
  13. 12 Jan, 2006 5 commits
  14. 15 Nov, 2005 1 commit
    • Jacob Shin's avatar
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      Jacob Shin authored
      
      
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
      This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
      The user may interface through sysfs files in order to change the threshold configuration.
      
      bank%d/error_count - reads current error count, write to clear.
      bank%d/interrupt_enable - set/clear interrupt enable.
      bank%d/threshold_limit - read/write the threshold limit.
      
      APIC vector 0xF9 in hw_irq.h.
      5 software defined bank ids in mce.h.
      new apic.c function to setup threshold apic lvt.
      defaults to interrupt off, count enabled, and threshold limit max.
      sysfs interface created on /sys/devices/system/threshold.
      
      AK: added some ifdefs to make it compile on UP
      Signed-off-by: default avatarJacob Shin <jacob.shin@amd.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      89b831ef
  15. 12 Sep, 2005 5 commits
  16. 25 Jun, 2005 2 commits
  17. 17 May, 2005 2 commits
    • Andi Kleen's avatar
      [PATCH] x86_64: Collected NMI watchdog fixes. · 75152114
      Andi Kleen authored
      
      
      Collected NMI watchdog fixes.
      
      - Fix call of check_nmi_watchdog
      
      - Remove earlier move of check_nmi_watchdog to later.  It does not fix the
        race it was supposed to fix fully.
      
      - Remove unused P6 definitions
      
      - Add support for performance counter based watchdog on P4 systems.
      
        This allows to run it only once per second, which saves some CPU time.
        Previously it would run at 1000Hz, which was too much.
      
        Code ported from i386
      
        Make this the default on Intel systems.
      
      - Use check_nmi_watchdog with local APIC based nmi
      
      - Fix race in touch_nmi_watchdog
      
      - Fix bug that caused incorrect performance counters to be programmed in a
        few cases on K8.
      
      - Remove useless check for local APIC
      
      - Use local_t and per_cpu variables for per CPU data.
      
      - Keep other CPUs busy during check_nmi_watchdog to make sure they really
        tick when in lapic mode.
      
      - Only check CPUs that are actually online.
      
      - Various other fixes.
      
      - Fix fallback path when MSRs are unimplemented
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      75152114
    • Suresh Siddha's avatar
      [PATCH] x86_64: Fix OEM hpet check · 376ec33f
      Suresh Siddha authored
      
      
      Use bitmap_zero instead of bitmap_empty to initialise cpu mask This makes it
      actually run reliable instead of relying on stack state.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      376ec33f
  18. 16 Apr, 2005 2 commits