1. 02 Mar, 2017 2 commits
  2. 28 Feb, 2017 2 commits
  3. 15 Feb, 2017 4 commits
  4. 10 Feb, 2017 1 commit
    • Christopher Covington's avatar
      arm64: Work around Falkor erratum 1003 · 38fd94b0
      Christopher Covington authored
      
      
      The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
      using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
      is triggered, page table entries using the new translation table base
      address (BADDR) will be allocated into the TLB using the old ASID. All
      circumstances leading to the incorrect ASID being cached in the TLB arise
      when software writes TTBRx_EL1[ASID] and TTBRx_EL1[BADDR], a memory
      operation is in the process of performing a translation using the specific
      TTBRx_EL1 being written, and the memory operation uses a translation table
      descriptor designated as non-global. EL2 and EL3 code changing the EL1&0
      ASID is not subject to this erratum because hardware is prohibited from
      performing translations from an out-of-context translation regime.
      
      Consider the following pseudo code.
      
        write new BADDR and ASID values to TTBRx_EL1
      
      Replacing the above sequence with the one below will ensure that no TLB
      entries with an incorrect ASID are used by software.
      
        write reserved value to TTBRx_EL1[ASID]
        ISB
        write new value to TTBRx_EL1[BADDR]
        ISB
        write new value to TTBRx_EL1[ASID]
        ISB
      
      When the above sequence is used, page table entries using the new BADDR
      value may still be incorrectly allocated into the TLB using the reserved
      ASID. Yet this will not reduce functionality, since TLB entries incorrectly
      tagged with the reserved ASID will never be hit by a later instruction.
      
      Based on work by Shanker Donthineni <shankerd@codeaurora.org>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarChristopher Covington <cov@codeaurora.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      38fd94b0
  5. 09 Feb, 2017 2 commits
  6. 08 Feb, 2017 1 commit
  7. 07 Feb, 2017 1 commit
  8. 03 Feb, 2017 3 commits
    • Andy Gross's avatar
      firmware: qcom: scm: Fix interrupted SCM calls · 82bcd087
      Andy Gross authored
      This patch adds a Qualcomm specific quirk to the arm_smccc_smc call.
      
      On Qualcomm ARM64 platforms, the SMC call can return before it has
      completed.  If this occurs, the call can be restarted, but it requires
      using the returned session ID value from the interrupted SMC call.
      
      The quirk stores off the session ID from the interrupted call in the
      quirk structure so that it can be used by the caller.
      
      This patch folds in a fix given by Sricharan R:
      https://lkml.org/lkml/2016/9/28/272
      
      Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      82bcd087
    • Andy Gross's avatar
      arm: kernel: Add SMC structure parameter · 680a0873
      Andy Gross authored
      
      
      This patch adds a quirk parameter to the arm_smccc_(smc/hvc) calls.
      The quirk structure allows for specialized SMC operations due to SoC
      specific requirements.  The current arm_smccc_(smc/hvc) is renamed and
      macros are used instead to specify the standard arm_smccc_(smc/hvc) or
      the arm_smccc_(smc/hvc)_quirk function.
      
      This patch and partial implementation was suggested by Will Deacon.
      Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      680a0873
    • Ard Biesheuvel's avatar
      efi: arm64: Add vmlinux debug link to the Image binary · 757b435a
      Ard Biesheuvel authored
      
      
      When building with debugging symbols, take the absolute path to the
      vmlinux binary and add it to the special PE/COFF debug table entry.
      This allows a debug EFI build to find the vmlinux binary, which is
      very helpful in debugging, given that the offset where the Image is
      first loaded by EFI is highly unpredictable.
      
      On implementations of UEFI that choose to implement it, this
      information is exposed via the EFI debug support table, which is a UEFI
      configuration table that is accessible both by the firmware at boot time
      and by the OS at runtime, and lists all PE/COFF images loaded by the
      system.
      
      The format of the NB10 Codeview entry is based on the definition used
      by EDK2, which is our primary reference when it comes to the use of
      PE/COFF in the context of UEFI firmware.
      Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      [will: use realpath instead of shell invocation, as discussed on list]
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      757b435a
  9. 02 Feb, 2017 3 commits
  10. 01 Feb, 2017 1 commit
    • Christopher Covington's avatar
      arm64: Work around Falkor erratum 1009 · d9ff80f8
      Christopher Covington authored
      
      
      During a TLB invalidate sequence targeting the inner shareable domain,
      Falkor may prematurely complete the DSB before all loads and stores using
      the old translation are observed. Instruction fetches are not subject to
      the conditions of this erratum. If the original code sequence includes
      multiple TLB invalidate instructions followed by a single DSB, onle one of
      the TLB instructions needs to be repeated to work around this erratum.
      While the erratum only applies to cases in which the TLBI specifies the
      inner-shareable domain (*IS form of TLBI) and the DSB is ISH form or
      stronger (OSH, SYS), this changes applies the workaround overabundantly--
      to local TLBI, DSB NSH sequences as well--for simplicity.
      
      Based on work by Shanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: default avatarChristopher Covington <cov@codeaurora.org>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      d9ff80f8
  11. 27 Jan, 2017 2 commits
    • Mark Rutland's avatar
      arm64: handle sys and undef traps consistently · 49f6cba6
      Mark Rutland authored
      
      
      If an EL0 instruction in the SYS class triggers an exception, do_sysintr
      looks for a sys64_hook matching the instruction, and if none is found,
      injects a SIGILL. This mirrors what we do for undefined instruction
      encodings in do_undefinstr, where we look for an undef_hook matching the
      instruction, and if none is found, inject a SIGILL.
      
      Over time, new SYS instruction encodings may be allocated. Prior to
      allocation, exceptions resulting from these would be handled by
      do_undefinstr, whereas after allocation these may be handled by
      do_sysintr.
      
      To ensure that we have consistent behaviour if and when this happens, it
      would be beneficial to have do_sysinstr fall back to do_undefinstr.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarSuzuki Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      49f6cba6
    • Prashanth Prakash's avatar
      arm64: skip register_cpufreq_notifier on ACPI-based systems · 606f4226
      Prashanth Prakash authored
      On ACPI based systems where the topology is setup using the API
      store_cpu_topology, at the moment we do not have necessary code
      to parse cpu capacity and handle cpufreq notifier, thus
      resulting in a kernel panic.
      
      Stack:
              init_cpu_capacity_callback+0xb4/0x1c8
              notifier_call_chain+0x5c/0xa0
              __blocking_notifier_call_chain+0x58/0xa0
              blocking_notifier_call_chain+0x3c/0x50
              cpufreq_set_policy+0xe4/0x328
              cpufreq_init_policy+0x80/0x100
              cpufreq_online+0x418/0x710
              cpufreq_add_dev+0x118/0x180
              subsys_interface_register+0xa4/0xf8
              cpufreq_register_driver+0x1c0/0x298
              cppc_cpufreq_init+0xdc/0x1000 [cppc_cpufreq]
              do_one_initcall+0x5c/0x168
              do_init_module+0x64/0x1e4
              load_module+0x130c/0x14d0
              SyS_finit_module+0x108/0x120
              el0_svc_naked+0x24/0x28
      
      Fixes: 7202bde8
      
       ("arm64: parse cpu capacity-dmips-mhz from DT")
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarPrashanth Prakash <pprakash@codeaurora.org>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      606f4226
  12. 26 Jan, 2017 2 commits
  13. 19 Jan, 2017 1 commit
    • Mark Rutland's avatar
      arm64: avoid returning from bad_mode · 7d9e8f71
      Mark Rutland authored
      Generally, taking an unexpected exception should be a fatal event, and
      bad_mode is intended to cater for this. However, it should be possible
      to contain unexpected synchronous exceptions from EL0 without bringing
      the kernel down, by sending a SIGILL to the task.
      
      We tried to apply this approach in commit 9955ac47
      
       ("arm64:
      don't kill the kernel on a bad esr from el0"), by sending a signal for
      any bad_mode call resulting from an EL0 exception.
      
      However, this also applies to other unexpected exceptions, such as
      SError and FIQ. The entry paths for these exceptions branch to bad_mode
      without configuring the link register, and have no kernel_exit. Thus, if
      we take one of these exceptions from EL0, bad_mode will eventually
      return to the original user link register value.
      
      This patch fixes this by introducing a new bad_el0_sync handler to cater
      for the recoverable case, and restoring bad_mode to its original state,
      whereby it calls panic() and never returns. The recoverable case
      branches to bad_el0_sync with a bl, and returns to userspace via the
      usual ret_to_user mechanism.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Fixes: 9955ac47
      
       ("arm64: don't kill the kernel on a bad esr from el0")
      Reported-by: default avatarMark Salter <msalter@redhat.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      7d9e8f71
  14. 18 Jan, 2017 4 commits
  15. 17 Jan, 2017 4 commits
    • Mark Rutland's avatar
      arm64: entry-ftrace.S: avoid open-coded {adr,ldr}_l · 829d2bd1
      Mark Rutland authored
      
      
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of these in entry-ftrace.S, removing open-coded
      sequences using adrp. This results in a minor code change, since a
      temporary register is not used when generating the address for some
      symbols, but this is fine, as the value of the temporary register is not
      used elsewhere.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      829d2bd1
    • Mark Rutland's avatar
      arm64: efi-entry.S: avoid open-coded adr_l · 526d10ae
      Mark Rutland authored
      
      
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of these in efi-entry.S, removing open-coded
      sequences using adrp.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Matt Fleming <matt@codeblueprint.co.uk>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      526d10ae
    • Mark Rutland's avatar
      arm64: head.S: avoid open-coded adr_l · 9bb00360
      Mark Rutland authored
      
      
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of adr_l these in head.S, removing an open-coded
      sequence using adrp.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9bb00360
    • Sudeep Holla's avatar
      arm64: cacheinfo: add support to override cache levels via device tree · 9a802431
      Sudeep Holla authored
      
      
      The cache hierarchy can be identified through Cache Level ID(CLIDR)
      architected system register. However in some cases it will provide
      only the number of cache levels that are integrated into the processor
      itself. In other words, it can't provide any information about the
      caches that are external and/or transparent.
      
      Some platforms require to export the information about all such external
      caches to the userspace applications via the sysfs interface.
      
      This patch adds support to override the cache levels using device tree
      to take such external non-architected caches into account.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Tested-by: default avatarTan Xiaojun <tanxiaojun@huawei.com>
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9a802431
  16. 13 Jan, 2017 1 commit
  17. 12 Jan, 2017 4 commits
  18. 10 Jan, 2017 2 commits