1. 19 Mar, 2020 1 commit
    • Greentime Hu's avatar
      riscv: fix the IPI missing issue in nommu mode · 3384b043
      Greentime Hu authored
      
      
      This patch fixes the IPI(inner processor interrupt) missing issue. It
      failed because it used hartid_mask to iterate for_each_cpu(), however the
      cpu_mask and hartid_mask may not be always the same. It will never send the
      IPI to hartid 4 because it will be skipped in for_each_cpu loop in my case.
      
      We can reproduce this case in Qemu sifive_u machine by this command.
      qemu-system-riscv64 -nographic -smp 5 -m 1G -M sifive_u -kernel \
      arch/riscv/boot/loader
      
      It will hang in csd_lock_wait(csd) because the csd_unlock(csd) is not
      called. It is not called because hartid 4 doesn't receive the IPI to
      release this lock. The caller hart doesn't send the IPI to hartid 4 is
      because of hartid 4 is skipped in for_each_cpu(). It will be skipped is
      because "(cpu) < nr_cpu_ids" is not true. The hartid is 4 and nr_cpu_ids
      is 4. Therefore it should use cpumask in for_each_cpu() instead of
      hartid_mask.
      
              /* Send a message to all CPUs in the map */
              arch_send_call_function_ipi_mask(cfd->cpumask_ipi);
      
              if (wait) {
                      for_each_cpu(cpu, cfd->cpumask) {
                              call_single_data_t *csd;
      			csd = per_cpu_ptr(cfd->csd, cpu);
                              csd_lock_wait(csd);
                      }
              }
      
              for ((cpu) = -1;                                \
                      (cpu) = cpumask_next((cpu), (mask)),    \
                      (cpu) < nr_cpu_ids;)
      
      It could boot to login console after this patch applied.
      
      Fixes: b2d36b5668f6 ("riscv: provide native clint access for M-mode")
      Signed-off-by: default avatarGreentime Hu <greentime.hu@sifive.com>
      Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
      3384b043
  2. 17 Nov, 2019 1 commit
    • Christoph Hellwig's avatar
      riscv: provide native clint access for M-mode · fcdc6537
      Christoph Hellwig authored
      
      
      RISC-V has the concept of a cpu level interrupt controller.  The
      interface for it is split between a standardized part that is exposed
      as bits in the mstatus/sstatus register and the mie/mip/sie/sip
      CRS.  But the bit to actually trigger IPIs is not standardized and
      just mentioned as implementable using MMIO.
      
      Add support for IPIs using MMIO using the SiFive clint layout (which
      is also shared by Ariane, Kendryte and the Qemu virt platform).
      Additionally the MMIO block also supports the time value and timer
      compare registers, so they are also set up using the same OF node.
      Support for other layouts should also be relatively easy to add in the
      future.
      Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
      Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
      [paul.walmsley@sifive.com: update include guard format; fix checkpatch
       issues; minor commit message cleanup]
      Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
      fcdc6537