1. 28 Feb, 2017 1 commit
  2. 06 Jun, 2016 1 commit
  3. 31 May, 2016 1 commit
    • Chris Brand's avatar
      ARM: BCM: modify Broadcom CPU enable method · 6585cb5a
      Chris Brand authored
      Commit 84320e1a
      
      
      ("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the
      "secondary-boot-reg" property from the "cpus" node to the individual "cpu"
      nodes but negelected to actually support multiple "secondary-boot-reg"
      properties.
      
      This patchset rectifies that omission. Note that the behaviour is changed
      slightly in that the "secondary-boot-reg" property is now read in
      smp_boot_secondary() rather than smp_prepare_cpus(). This means that any
      omissions will now only be reported when and if the cpu in question is being
      brought up. It also means that an omission for one cpu will not force
      uniprocessor mode.
      Signed-off-by: default avatarChris Brand <chris.brand@broadcom.com>
      Reviewed-and-Tested-by: default avatarJon Mason <jon.mason@broadcom.com>
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      6585cb5a
  4. 01 Feb, 2016 1 commit
  5. 07 Dec, 2015 2 commits
  6. 01 Dec, 2015 1 commit
  7. 28 Jul, 2014 1 commit
    • Alex Elder's avatar
      ARM: add SMP support for Broadcom mobile SoCs · 9a5a110e
      Alex Elder authored
      
      
      This patch adds SMP support for BCM281XX and BCM21664 family SoCs.
      
      This feature is controlled with a distinct config option such that
      an SMP-enabled multi-v7 binary can be configured to run these SoCs
      in uniprocessor mode.  Since this SMP functionality is used for
      multiple Broadcom mobile chip families the config option is called
      ARCH_BCM_MOBILE_SMP (for lack of a better name).
      
      On SoCs of this type, the secondary core is not held in reset on
      power-on.  Instead it loops in a ROM-based holding pen.  To release
      it, one must write into a special register a jump address whose
      low-order bits have been replaced with a secondary core's id, then
      trigger an event with SEV.  On receipt of an event, the ROM code
      will examine the register's contents, and if the low-order bits
      match its cpu id, it will clear them and write the value back to the
      register just prior to jumping to the address specified.
      
      The location of the special register is defined in the device tree
      using a "secondary-boot-reg" property in a node whose "enable-method"
      matches.
      
      Derived from code originally provided by Ray Jui <rjui@broadcom.com>
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarMatt Porter <mporter@linaro.org>
      9a5a110e