i915_gem.c 135 KB
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/*
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 * Copyright © 2008-2015 Intel Corporation
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

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#include <drm/drmP.h>
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#include <drm/drm_vma_manager.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_vgpu.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include "intel_frontbuffer.h"
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#include "intel_mocs.h"
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#include <linux/dma-fence-array.h>
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#include <linux/kthread.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>
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#include <linux/slab.h>
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#include <linux/stop_machine.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/dma-buf.h>
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static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
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static bool cpu_cache_is_coherent(struct drm_device *dev,
				  enum i915_cache_level level)
{
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	return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
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}

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static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
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	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return false;

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	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
		return true;

	return obj->pin_display;
}

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static int
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insert_mappable_node(struct i915_ggtt *ggtt,
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                     struct drm_mm_node *node, u32 size)
{
	memset(node, 0, sizeof(*node));
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	return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
					   size, 0, I915_COLOR_UNEVICTABLE,
					   0, ggtt->mappable_end,
					   DRM_MM_INSERT_LOW);
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}

static void
remove_mappable_node(struct drm_mm_node *node)
{
	drm_mm_remove_node(node);
}

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/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
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				  u64 size)
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{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
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				     u64 size)
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{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

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static int
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i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
	int ret;

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	might_sleep();

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	if (!i915_reset_in_progress(error))
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		return 0;

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	/*
	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
	 * userspace. If it takes that long something really bad is going on and
	 * we should simply try to bail out and fail as gracefully as possible.
	 */
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	ret = wait_event_interruptible_timeout(error->reset_queue,
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					       !i915_reset_in_progress(error),
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					       I915_RESET_TIMEOUT);
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	if (ret == 0) {
		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
		return -EIO;
	} else if (ret < 0) {
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		return ret;
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	} else {
		return 0;
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	}
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}

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int i915_mutex_lock_interruptible(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	int ret;

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	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
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	if (ret)
		return ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	return 0;
}
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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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			    struct drm_file *file)
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{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct i915_ggtt *ggtt = &dev_priv->ggtt;
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	struct drm_i915_gem_get_aperture *args = data;
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	struct i915_vma *vma;
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	size_t pinned;
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	pinned = 0;
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	mutex_lock(&dev->struct_mutex);
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	list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
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		if (i915_vma_is_pinned(vma))
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			pinned += vma->node.size;
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	list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
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		if (i915_vma_is_pinned(vma))
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			pinned += vma->node.size;
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	mutex_unlock(&dev->struct_mutex);
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	args->aper_size = ggtt->base.total;
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	args->aper_available_size = args->aper_size - pinned;
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	return 0;
}

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static struct sg_table *
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i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
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{
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	struct address_space *mapping = obj->base.filp->f_mapping;
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	drm_dma_handle_t *phys;
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	struct sg_table *st;
	struct scatterlist *sg;
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	char *vaddr;
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	int i;
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	if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
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		return ERR_PTR(-EINVAL);
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	/* Always aligning to the object size, allows a single allocation
	 * to handle all possible callers, and given typical object sizes,
	 * the alignment of the buddy allocation will naturally match.
	 */
	phys = drm_pci_alloc(obj->base.dev,
			     obj->base.size,
			     roundup_pow_of_two(obj->base.size));
	if (!phys)
		return ERR_PTR(-ENOMEM);

	vaddr = phys->vaddr;
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	for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
		struct page *page;
		char *src;

		page = shmem_read_mapping_page(mapping, i);
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		if (IS_ERR(page)) {
			st = ERR_CAST(page);
			goto err_phys;
		}
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		src = kmap_atomic(page);
		memcpy(vaddr, src, PAGE_SIZE);
		drm_clflush_virt_range(vaddr, PAGE_SIZE);
		kunmap_atomic(src);

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		put_page(page);
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		vaddr += PAGE_SIZE;
	}

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	i915_gem_chipset_flush(to_i915(obj->base.dev));
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	st = kmalloc(sizeof(*st), GFP_KERNEL);
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	if (!st) {
		st = ERR_PTR(-ENOMEM);
		goto err_phys;
	}
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	if (sg_alloc_table(st, 1, GFP_KERNEL)) {
		kfree(st);
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		st = ERR_PTR(-ENOMEM);
		goto err_phys;
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	}

	sg = st->sgl;
	sg->offset = 0;
	sg->length = obj->base.size;
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	sg_dma_address(sg) = phys->busaddr;
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	sg_dma_len(sg) = obj->base.size;

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	obj->phys_handle = phys;
	return st;

err_phys:
	drm_pci_free(obj->base.dev, phys);
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	return st;
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}

static void
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__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
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				struct sg_table *pages,
				bool needs_clflush)
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{
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	GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
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	if (obj->mm.madv == I915_MADV_DONTNEED)
		obj->mm.dirty = false;
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	if (needs_clflush &&
	    (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
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	    !cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
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		drm_clflush_sg(pages);
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	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
}

static void
i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
			       struct sg_table *pages)
{
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	__i915_gem_object_release_shmem(obj, pages, false);
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	if (obj->mm.dirty) {
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		struct address_space *mapping = obj->base.filp->f_mapping;
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		char *vaddr = obj->phys_handle->vaddr;
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		int i;

		for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
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			struct page *page;
			char *dst;

			page = shmem_read_mapping_page(mapping, i);
			if (IS_ERR(page))
				continue;

			dst = kmap_atomic(page);
			drm_clflush_virt_range(vaddr, PAGE_SIZE);
			memcpy(dst, vaddr, PAGE_SIZE);
			kunmap_atomic(dst);

			set_page_dirty(page);
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			if (obj->mm.madv == I915_MADV_WILLNEED)
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				mark_page_accessed(page);
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			put_page(page);
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			vaddr += PAGE_SIZE;
		}
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		obj->mm.dirty = false;
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	}

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	sg_free_table(pages);
	kfree(pages);
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	drm_pci_free(obj->base.dev, obj->phys_handle);
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}

static void
i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
{
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	i915_gem_object_unpin_pages(obj);
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}

static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
	.get_pages = i915_gem_object_get_pages_phys,
	.put_pages = i915_gem_object_put_pages_phys,
	.release = i915_gem_object_release_phys,
};

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static const struct drm_i915_gem_object_ops i915_gem_object_ops;

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int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
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{
	struct i915_vma *vma;
	LIST_HEAD(still_in_list);
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	int ret;

	lockdep_assert_held(&obj->base.dev->struct_mutex);
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	/* Closed vma are removed from the obj->vma_list - but they may
	 * still have an active binding on the object. To remove those we
	 * must wait for all rendering to complete to the object (as unbinding
	 * must anyway), and retire the requests.
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	 */
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	ret = i915_gem_object_wait(obj,
				   I915_WAIT_INTERRUPTIBLE |
				   I915_WAIT_LOCKED |
				   I915_WAIT_ALL,
				   MAX_SCHEDULE_TIMEOUT,
				   NULL);
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	if (ret)
		return ret;

	i915_gem_retire_requests(to_i915(obj->base.dev));

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	while ((vma = list_first_entry_or_null(&obj->vma_list,
					       struct i915_vma,
					       obj_link))) {
		list_move_tail(&vma->obj_link, &still_in_list);
		ret = i915_vma_unbind(vma);
		if (ret)
			break;
	}
	list_splice(&still_in_list, &obj->vma_list);

	return ret;
}

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static long
i915_gem_object_wait_fence(struct dma_fence *fence,
			   unsigned int flags,
			   long timeout,
			   struct intel_rps_client *rps)
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{
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	struct drm_i915_gem_request *rq;
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	BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
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	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
		return timeout;

	if (!dma_fence_is_i915(fence))
		return dma_fence_wait_timeout(fence,
					      flags & I915_WAIT_INTERRUPTIBLE,
					      timeout);

	rq = to_request(fence);
	if (i915_gem_request_completed(rq))
		goto out;

	/* This client is about to stall waiting for the GPU. In many cases
	 * this is undesirable and limits the throughput of the system, as
	 * many clients cannot continue processing user input/output whilst
	 * blocked. RPS autotuning may take tens of milliseconds to respond
	 * to the GPU load and thus incurs additional latency for the client.
	 * We can circumvent that by promoting the GPU frequency to maximum
	 * before we wait. This makes the GPU throttle up much more quickly
	 * (good for benchmarks and user experience, e.g. window animations),
	 * but at a cost of spending more power processing the workload
	 * (bad for battery). Not all clients even want their results
	 * immediately and for them we should just let the GPU select its own
	 * frequency to maximise efficiency. To prevent a single client from
	 * forcing the clocks too high for the whole system, we only allow
	 * each client to waitboost once in a busy period.
	 */
	if (rps) {
		if (INTEL_GEN(rq->i915) >= 6)
			gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
		else
			rps = NULL;
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	}

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	timeout = i915_wait_request(rq, flags, timeout);

out:
	if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
		i915_gem_request_retire_upto(rq);

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	if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
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		/* The GPU is now idle and this client has stalled.
		 * Since no other client has submitted a request in the
		 * meantime, assume that this client is the only one
		 * supplying work to the GPU but is unable to keep that
		 * work supplied because it is waiting. Since the GPU is
		 * then never kept fully busy, RPS autoclocking will
		 * keep the clocks relatively low, causing further delays.
		 * Compensate by giving the synchronous client credit for
		 * a waitboost next time.
		 */
		spin_lock(&rq->i915->rps.client_lock);
		list_del_init(&rps->link);
		spin_unlock(&rq->i915->rps.client_lock);
	}

	return timeout;
}

static long
i915_gem_object_wait_reservation(struct reservation_object *resv,
				 unsigned int flags,
				 long timeout,
				 struct intel_rps_client *rps)
{
	struct dma_fence *excl;

	if (flags & I915_WAIT_ALL) {
		struct dma_fence **shared;
		unsigned int count, i;
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		int ret;

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		ret = reservation_object_get_fences_rcu(resv,
							&excl, &count, &shared);
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		if (ret)
			return ret;

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		for (i = 0; i < count; i++) {
			timeout = i915_gem_object_wait_fence(shared[i],
							     flags, timeout,
							     rps);
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			if (timeout < 0)
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				break;
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			dma_fence_put(shared[i]);
		}

		for (; i < count; i++)
			dma_fence_put(shared[i]);
		kfree(shared);
	} else {
		excl = reservation_object_get_excl_rcu(resv);
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	}

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	if (excl && timeout >= 0)
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		timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);

	dma_fence_put(excl);

	return timeout;
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}

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static void __fence_set_priority(struct dma_fence *fence, int prio)
{
	struct drm_i915_gem_request *rq;
	struct intel_engine_cs *engine;

	if (!dma_fence_is_i915(fence))
		return;

	rq = to_request(fence);
	engine = rq->engine;
	if (!engine->schedule)
		return;

	engine->schedule(rq, prio);
}

static void fence_set_priority(struct dma_fence *fence, int prio)
{
	/* Recurse once into a fence-array */
	if (dma_fence_is_array(fence)) {
		struct dma_fence_array *array = to_dma_fence_array(fence);
		int i;

		for (i = 0; i < array->num_fences; i++)
			__fence_set_priority(array->fences[i], prio);
	} else {
		__fence_set_priority(fence, prio);
	}
}

int
i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
			      unsigned int flags,
			      int prio)
{
	struct dma_fence *excl;

	if (flags & I915_WAIT_ALL) {
		struct dma_fence **shared;
		unsigned int count, i;
		int ret;

		ret = reservation_object_get_fences_rcu(obj->resv,
							&excl, &count, &shared);
		if (ret)
			return ret;

		for (i = 0; i < count; i++) {
			fence_set_priority(shared[i], prio);
			dma_fence_put(shared[i]);
		}

		kfree(shared);
	} else {
		excl = reservation_object_get_excl_rcu(obj->resv);
	}

	if (excl) {
		fence_set_priority(excl, prio);
		dma_fence_put(excl);
	}
	return 0;
}

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/**
 * Waits for rendering to the object to be completed
 * @obj: i915 gem object
 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
 * @timeout: how long to wait
 * @rps: client (user process) to charge for any waitboosting
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 */
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int
i915_gem_object_wait(struct drm_i915_gem_object *obj,
		     unsigned int flags,
		     long timeout,
		     struct intel_rps_client *rps)
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{
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	might_sleep();
#if IS_ENABLED(CONFIG_LOCKDEP)
	GEM_BUG_ON(debug_locks &&
		   !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
		   !!(flags & I915_WAIT_LOCKED));
#endif
	GEM_BUG_ON(timeout < 0);
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	timeout = i915_gem_object_wait_reservation(obj->resv,
						   flags, timeout,
						   rps);
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	return timeout < 0 ? timeout : 0;
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}

static struct intel_rps_client *to_rps_client(struct drm_file *file)
{
	struct drm_i915_file_private *fpriv = file->driver_priv;

	return &fpriv->rps;
}

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int
i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
			    int align)
{
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	int ret;
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	if (align > obj->base.size)
		return -EINVAL;
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	if (obj->ops == &i915_gem_phys_ops)
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		return 0;

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	if (obj->mm.madv != I915_MADV_WILLNEED)
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		return -EFAULT;

	if (obj->base.filp == NULL)
		return -EINVAL;

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	ret = i915_gem_object_unbind(obj);
	if (ret)
		return ret;

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	__i915_gem_object_put_pages(obj, I915_MM_NORMAL);
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	if (obj->mm.pages)
		return -EBUSY;
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	GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
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	obj->ops = &i915_gem_phys_ops;

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	ret = i915_gem_object_pin_pages(obj);
	if (ret)
		goto err_xfer;

	return 0;

err_xfer:
	obj->ops = &i915_gem_object_ops;
	return ret;
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}

static int
i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pwrite *args,
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		     struct drm_file *file)
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{
	void *vaddr = obj->phys_handle->vaddr + args->offset;
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	char __user *user_data = u64_to_user_ptr(args->data_ptr);
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	/* We manually control the domain here and pretend that it
	 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
	 */
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	intel_fb_obj_invalidate(obj, ORIGIN_CPU);
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	if (copy_from_user(vaddr, user_data, args->size))
		return -EFAULT;
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	drm_clflush_virt_range(vaddr, args->size);
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	i915_gem_chipset_flush(to_i915(obj->base.dev));
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	intel_fb_obj_flush(obj, false, ORIGIN_CPU);
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	return 0;
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}

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void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
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{
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	return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
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}

void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
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	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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	kmem_cache_free(dev_priv->objects, obj);
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}

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static int
i915_gem_create(struct drm_file *file,
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		struct drm_i915_private *dev_priv,
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		uint64_t size,
		uint32_t *handle_p)
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{
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	struct drm_i915_gem_object *obj;
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	int ret;
	u32 handle;
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	size = roundup(size, PAGE_SIZE);
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	if (size == 0)
		return -EINVAL;
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	/* Allocate the new object */
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	obj = i915_gem_object_create(dev_priv, size);
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	if (IS_ERR(obj))
		return PTR_ERR(obj);
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	ret = drm_gem_handle_create(file, &obj->base, &handle);
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	/* drop reference from allocate - handle holds it now */
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	i915_gem_object_put(obj);
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	if (ret)
		return ret;
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663
	*handle_p = handle;
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	return 0;
}

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int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
673
	args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
674
	args->size = args->pitch * args->height;
675
	return i915_gem_create(file, to_i915(dev),
676
			       args->size, &args->handle);
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}

/**
 * Creates a new mm object and returns a handle to it.
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 * @dev: drm device pointer
 * @data: ioctl data blob
 * @file: drm file pointer
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 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
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	struct drm_i915_private *dev_priv = to_i915(dev);
690
	struct drm_i915_gem_create *args = data;
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692
	i915_gem_flush_free_objects(dev_priv);
693

694
	return i915_gem_create(file, dev_priv,
695
			       args->size, &args->handle);
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}

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static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
			int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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static inline int
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__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
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			  int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
				       cpu_vaddr + cpu_offset,
				       this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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/*
 * Pins the specified object's pages and synchronizes the object with
 * GPU accesses. Sets needs_clflush to non-zero if the caller should
 * flush the object from the CPU cache.
 */
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
756
				    unsigned int *needs_clflush)
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{
	int ret;

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	lockdep_assert_held(&obj->base.dev->struct_mutex);
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762
	*needs_clflush = 0;
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	if (!i915_gem_object_has_struct_page(obj))
		return -ENODEV;
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	ret = i915_gem_object_wait(obj,
				   I915_WAIT_INTERRUPTIBLE |
				   I915_WAIT_LOCKED,
				   MAX_SCHEDULE_TIMEOUT,
				   NULL);
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	if (ret)
		return ret;

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	ret = i915_gem_object_pin_pages(obj);
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	if (ret)
		return ret;

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	i915_gem_object_flush_gtt_write_domain(obj);

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	/* If we're not in the cpu read domain, set ourself into the gtt
	 * read domain and manually flush cachelines (if required). This
	 * optimizes for the case when the gpu will dirty the data
	 * anyway again before the next pread happens.
	 */
	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
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		*needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
							obj->cache_level);
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	if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
		ret = i915_gem_object_set_to_cpu_domain(obj, false);
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		if (ret)
			goto err_unpin;

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		*needs_clflush = 0;
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	}

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	/* return with the pages pinned */
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	return 0;
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err_unpin:
	i915_gem_object_unpin_pages(obj);
	return ret;
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}

int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush)
{
	int ret;

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	lockdep_assert_held(&obj->base.dev->struct_mutex);

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	*needs_clflush = 0;
	if (!i915_gem_object_has_struct_page(obj))
		return -ENODEV;

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	ret = i915_gem_object_wait(obj,
				   I915_WAIT_INTERRUPTIBLE |
				   I915_WAIT_LOCKED |
				   I915_WAIT_ALL,
				   MAX_SCHEDULE_TIMEOUT,
				   NULL);
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	if (ret)
		return ret;

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	ret = i915_gem_object_pin_pages(obj);
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	if (ret)
		return ret;

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	i915_gem_object_flush_gtt_write_domain(obj);

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	/* If we're not in the cpu write domain, set ourself into the
	 * gtt write domain and manually flush cachelines (as required).
	 * This optimizes for the case when the gpu will use the data
	 * right away and we therefore have to clflush anyway.
	 */
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
		*needs_clflush |= cpu_write_needs_clflush(obj) << 1;

	/* Same trick applies to invalidate partially written cachelines read
	 * before writing.
	 */
	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
		*needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
							 obj->cache_level);

	if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
		ret = i915_gem_object_set_to_cpu_domain(obj, true);
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		if (ret)
			goto err_unpin;

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		*needs_clflush = 0;
	}

	if ((*needs_clflush & CLFLUSH_AFTER) == 0)
		obj->cache_dirty = true;

	intel_fb_obj_invalidate(obj, ORIGIN_CPU);
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	obj->mm.dirty = true;
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	/* return with the pages pinned */
860
	return 0;
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err_unpin:
	i915_gem_object_unpin_pages(obj);
	return ret;
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}

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static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
871
	if (unlikely(swizzled)) {
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		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;

		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);

		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}

}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
892
shmem_pread_slow(struct page *page, int offset, int length,
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		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

	vaddr = kmap(page);
	if (needs_clflush)
901
		shmem_clflush_swizzled_range(vaddr + offset, length,
902
					     page_do_bit17_swizzling);
903 904

	if (page_do_bit17_swizzling)
905
		ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
906
	else
907
		ret = __copy_to_user(user_data, vaddr + offset, length);
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	kunmap(page);

910
	return ret ? - EFAULT : 0;
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}

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static int
shmem_pread(struct page *page, int offset, int length, char __user *user_data,
	    bool page_do_bit17_swizzling, bool needs_clflush)
{
	int ret;

	ret = -ENODEV;
	if (!page_do_bit17_swizzling) {
		char *vaddr = kmap_atomic(page);

		if (needs_clflush)
			drm_clflush_virt_range(vaddr + offset, length);
		ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
		kunmap_atomic(vaddr);
	}
	if (ret == 0)
		return 0;

	return shmem_pread_slow(page, offset, length, user_data,
				page_do_bit17_swizzling, needs_clflush);
}

static int
i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pread *args)
{
	char __user *user_data;
	u64 remain;
	unsigned int obj_do_bit17_swizzling;
	unsigned int needs_clflush;
	unsigned int idx, offset;
	int ret;

	obj_do_bit17_swizzling = 0;
	if (i915_gem_object_needs_bit17_swizzle(obj))
		obj_do_bit17_swizzling = BIT(17);

	ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
	if (ret)
		return ret;

	ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
	mutex_unlock(&obj->base.dev->struct_mutex);
	if (ret)
		return ret;

	remain = args->size;
	user_data = u64_to_user_ptr(args->data_ptr);
	offset = offset_in_page(args->offset);
	for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
		struct page *page = i915_gem_object_get_page(obj, idx);
		int length;

		length = remain;
		if (offset + length > PAGE_SIZE)
			length = PAGE_SIZE - offset;

		ret = shmem_pread(page, offset, length, user_data,
				  page_to_phys(page) & obj_do_bit17_swizzling,
				  needs_clflush);
		if (ret)
			break;

		remain -= length;
		user_data += length;
		offset = 0;
	}

	i915_gem_obj_finish_shmem_access(obj);
	return ret;
}

static inline bool
gtt_user_read(struct io_mapping *mapping,
	      loff_t base, int offset,
	      char __user *user_data, int length)
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{
	void *vaddr;
991
	unsigned long unwritten;
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	/* We can use the cpu mem copy function because this is X86. */
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	vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
	unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
	io_mapping_unmap_atomic(vaddr);
	if (unwritten) {
		vaddr = (void __force *)
			io_mapping_map_wc(mapping, base, PAGE_SIZE);
		unwritten = copy_to_user(user_data, vaddr + offset, length);
		io_mapping_unmap(vaddr);
	}
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	return unwritten;
}

static int
1007 1008
i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
		   const struct drm_i915_gem_pread *args)
1009
{
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	struct drm_i915_private *i915 = to_i915(obj->base.dev);
	struct i915_ggtt *ggtt = &i915->ggtt;
1012
	struct drm_mm_node node;
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	struct i915_vma *vma;
	void __user *user_data;
	u64 remain, offset;
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	int ret;

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	ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
	if (ret)
		return ret;

	intel_runtime_pm_get(i915);
	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
				       PIN_MAPPABLE | PIN_NONBLOCK);
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	if (!IS_ERR(vma)) {
		node.start = i915_ggtt_offset(vma);
		node.allocated = false;
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		ret = i915_vma_put_fence(vma);
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		if (ret) {
			i915_vma_unpin(vma);
			vma = ERR_PTR(ret);
		}
	}
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1034
	if (IS_ERR(vma)) {
1035
		ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1036
		if (ret)
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			goto out_unlock;
		GEM_BUG_ON(!node.allocated);
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	}

	ret = i915_gem_object_set_to_gtt_domain(obj, false);
	if (ret)
		goto out_unpin;

1045
	mutex_unlock(&i915->drm.struct_mutex);
1046

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	user_data = u64_to_user_ptr(args->data_ptr);
	remain = args->size;
	offset = args->offset;
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	while (remain > 0) {
		/* Operation in this page
		 *
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
		 */
		u32 page_base = node.start;
		unsigned page_offset = offset_in_page(offset);
		unsigned page_length = PAGE_SIZE - page_offset;
		page_length = remain < page_length ? remain : page_length;
		if (node.allocated) {
			wmb();
			ggtt->base.insert_page(&ggtt->base,
					       i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1066
					       node.start, I915_CACHE_NONE, 0);
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			wmb();
		} else {
			page_base += offset & PAGE_MASK;
		}
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		if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
				  user_data, page_length)) {
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			ret = -EFAULT;
			break;
		}

		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}

1083
	mutex_lock(&i915->drm.struct_mutex);
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out_unpin:
	if (node.allocated) {
		wmb();
		ggtt->base.clear_range(&ggtt->base,
1088
				       node.start, node.size);
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		remove_mappable_node(&node);
	} else {
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1091
		i915_vma_unpin(vma);
1092
	}
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out_unlock:
	intel_runtime_pm_put(i915);
	mutex_unlock(&i915->drm.struct_mutex);
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	return ret;
}

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/**
 * Reads data from the object referenced by handle.
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 * @dev: drm device pointer
 * @data: ioctl data blob
 * @file: drm file pointer
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 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1110
		     struct drm_file *file)
1111 1112
{
	struct drm_i915_gem_pread *args = data;
1113
	struct drm_i915_gem_object *obj;
1114
	int ret;
1115

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	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_WRITE,
1120
		       u64_to_user_ptr(args->data_ptr),
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		       args->size))
		return -EFAULT;

1124
	obj = i915_gem_object_lookup(file, args->handle);
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	if (!obj)
		return -ENOENT;
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1128
	/* Bounds check source.  */
1129
	if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1130
		ret = -EINVAL;
1131
		goto out;
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	}

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1134 1135
	trace_i915_gem_object_pread(obj, args->offset, args->size);

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	ret = i915_gem_object_wait(obj,
				   I915_WAIT_INTERRUPTIBLE,
				   MAX_SCHEDULE_TIMEOUT,
				   to_rps_client(file));
1140
	if (ret)
1141
		goto out;
1142

1143
	ret = i915_gem_object_pin_pages(obj);
1144
	if (ret)
1145
		goto out;
1146

1147
	ret = i915_gem_shmem_pread(obj, args);
1148
	if (ret == -EFAULT || ret == -ENODEV)
1149
		ret = i915_gem_gtt_pread(obj, args);
1150

1151 1152
	i915_gem_object_unpin_pages(obj);
out:
1153
	i915_gem_object_put(obj);
1154
	return ret;
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}

1157 1158
/* This is the fast write path which cannot handle
 * page faults in the source data
1159
 */
1160

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static inline bool
ggtt_write(struct io_mapping *mapping,
	   loff_t base, int offset,
	   char __user *user_data, int length)
1165
{
1166
	void *vaddr;
1167
	unsigned long unwritten;
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1169
	/* We can use the cpu mem copy function because this is X86. */
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	vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
	unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
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						      user_data, length);
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	io_mapping_unmap_atomic(vaddr);
	if (unwritten) {
		vaddr = (void __force *)
			io_mapping_map_wc(mapping, base, PAGE_SIZE);
		unwritten = copy_from_user(vaddr + offset, user_data, length);
		io_mapping_unmap(vaddr);
	}
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	return unwritten;
}

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/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
1187
 * @obj: i915 GEM object
1188
 * @args: pwrite arguments structure
1189
 */
1190
static int
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i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_pwrite *args)
1193
{
1194
	struct drm_i915_private *i915 = to_i915(obj->base.dev);
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	struct i915_ggtt *ggtt = &i915->ggtt;
	struct drm_mm_node node;
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	struct i915_vma *vma;
	u64 remain, offset;
	void __user *user_data;
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	int ret;
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	ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
	if (ret)
		return ret;
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1205

1206
	intel_runtime_pm_get(i915);
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1207
	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
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				       PIN_MAPPABLE | PIN_NONBLOCK);
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	if (!IS_ERR(vma)) {
		node.start = i915_ggtt_offset(vma);
		node.allocated = false;
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		ret = i915_vma_put_fence(vma);