Commit 4a453314 authored by Rahul Sharma's avatar Rahul Sharma Committed by Mike Turquette

clk/exynos5250: add mout_hdmi mux clock for hdmi

hdmi driver needs to change the parent of hdmi clock
frequently between pixel clock and hdmiphy clock. hdmiphy is
not stable after power on and for a short interval while changing
the phy configuration. For this duration pixel clock is used to
clock hdmi.

This patch is exposing the mux for changing parent.
Signed-off-by: default avatarRahul Sharma <>
Signed-off-by: default avatarMike Turquette <>
parent 93b10d1b
......@@ -159,6 +159,14 @@ clock which they consume.
hdmi 344
g2d 345
[Clock Muxes]
Clock ID
mout_hdmi 1024
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
......@@ -102,6 +102,9 @@ enum exynos5250_clks {
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
/* mux clocks */
mout_hdmi = 1024,
......@@ -234,7 +237,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
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