Commit 86b6a203 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher

drm/amd/display: dce120 to dce ipp refactor

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 50db413d
......@@ -7,7 +7,7 @@
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o
dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
......
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCE_DCE_IPP_H_
#define _DCE_DCE_IPP_H_
#include "ipp.h"
#define TO_DCE_IPP(ipp)\
container_of(ipp, struct dce_ipp, base)
#define IPP_COMMON_REG_LIST_DCE_BASE(id) \
SRI(CUR_UPDATE, DCP, id), \
SRI(CUR_CONTROL, DCP, id), \
SRI(CUR_POSITION, DCP, id), \
SRI(CUR_HOT_SPOT, DCP, id), \
SRI(CUR_COLOR1, DCP, id), \
SRI(CUR_COLOR2, DCP, id), \
SRI(CUR_SIZE, DCP, id), \
SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
SRI(CUR_SURFACE_ADDRESS, DCP, id), \
SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
SRI(INPUT_GAMMA_CONTROL, DCP, id), \
SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
SRI(DC_LUT_RW_MODE, DCP, id), \
SRI(DC_LUT_CONTROL, DCP, id), \
SRI(DC_LUT_RW_INDEX, DCP, id), \
SRI(DC_LUT_SEQ_COLOR, DCP, id), \
SRI(DEGAMMA_CONTROL, DCP, id)
#define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \
IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
#define IPP_REG_FIELD_LIST(type) \
type CURSOR_UPDATE_LOCK; \
type CURSOR_EN; \
type CURSOR_X_POSITION; \
type CURSOR_Y_POSITION; \
type CURSOR_HOT_SPOT_X; \
type CURSOR_HOT_SPOT_Y; \
type CURSOR_MODE; \
type CURSOR_2X_MAGNIFY; \
type CUR_INV_TRANS_CLAMP; \
type CUR_COLOR1_BLUE; \
type CUR_COLOR1_GREEN; \
type CUR_COLOR1_RED; \
type CUR_COLOR2_BLUE; \
type CUR_COLOR2_GREEN; \
type CUR_COLOR2_RED; \
type CURSOR_WIDTH; \
type CURSOR_HEIGHT; \
type CURSOR_SURFACE_ADDRESS_HIGH; \
type CURSOR_SURFACE_ADDRESS; \
type GRPH_PRESCALE_BYPASS; \
type GRPH_PRESCALE_SCALE_R; \
type GRPH_PRESCALE_BIAS_R; \
type GRPH_PRESCALE_SCALE_G; \
type GRPH_PRESCALE_BIAS_G; \
type GRPH_PRESCALE_SCALE_B; \
type GRPH_PRESCALE_BIAS_B; \
type GRPH_INPUT_GAMMA_MODE; \
type DCP_LUT_MEM_PWR_DIS; \
type DC_LUT_WRITE_EN_MASK; \
type DC_LUT_RW_MODE; \
type DC_LUT_DATA_R_FORMAT; \
type DC_LUT_DATA_G_FORMAT; \
type DC_LUT_DATA_B_FORMAT; \
type DC_LUT_RW_INDEX; \
type DC_LUT_SEQ_COLOR; \
type GRPH_DEGAMMA_MODE; \
type CURSOR_DEGAMMA_MODE; \
type CURSOR2_DEGAMMA_MODE
struct dce_ipp_shift {
IPP_REG_FIELD_LIST(uint8_t);
};
struct dce_ipp_mask {
IPP_REG_FIELD_LIST(uint32_t);
};
struct dce_ipp_registers {
uint32_t CUR_UPDATE;
uint32_t CUR_CONTROL;
uint32_t CUR_POSITION;
uint32_t CUR_HOT_SPOT;
uint32_t CUR_COLOR1;
uint32_t CUR_COLOR2;
uint32_t CUR_SIZE;
uint32_t CUR_SURFACE_ADDRESS_HIGH;
uint32_t CUR_SURFACE_ADDRESS;
uint32_t PRESCALE_GRPH_CONTROL;
uint32_t PRESCALE_VALUES_GRPH_R;
uint32_t PRESCALE_VALUES_GRPH_G;
uint32_t PRESCALE_VALUES_GRPH_B;
uint32_t INPUT_GAMMA_CONTROL;
uint32_t DCFE_MEM_PWR_CTRL;
uint32_t DC_LUT_WRITE_EN_MASK;
uint32_t DC_LUT_RW_MODE;
uint32_t DC_LUT_CONTROL;
uint32_t DC_LUT_RW_INDEX;
uint32_t DC_LUT_SEQ_COLOR;
uint32_t DEGAMMA_CONTROL;
};
struct dce_ipp {
struct input_pixel_processor base;
const struct dce_ipp_registers *regs;
const struct dce_ipp_shift *ipp_shift;
const struct dce_ipp_mask *ipp_mask;
};
void dce_ipp_construct(struct dce_ipp *ipp_dce,
struct dc_context *ctx,
int inst,
const struct dce_ipp_registers *regs,
const struct dce_ipp_shift *ipp_shift,
const struct dce_ipp_mask *ipp_mask);
#endif /* _DCE_DCE_IPP_H_ */
......@@ -369,7 +369,7 @@ struct dce_transform {
bool prescaler_on;
};
bool dce_transform_construct(struct dce_transform *xfm110,
bool dce_transform_construct(struct dce_transform *xfm_dce,
struct dc_context *ctx,
uint32_t inst,
const struct dce_transform_registers *regs,
......
......@@ -59,7 +59,7 @@ void dce110_ipp_cursor_set_attributes(
const struct dc_cursor_attributes *attributes);
/* DEGAMMA RELATED */
bool dce110_ipp_set_degamma(
void dce110_ipp_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode);
......
......@@ -66,7 +66,7 @@
bool dce110_ipp_set_degamma(
void dce110_ipp_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode)
{
......@@ -82,8 +82,6 @@ bool dce110_ipp_set_degamma(
GRPH_DEGAMMA_MODE, degamma_type,
CURSOR_DEGAMMA_MODE, degamma_type,
CURSOR2_DEGAMMA_MODE, degamma_type);
return true;
}
void dce110_ipp_program_prescale(
......
......@@ -4,7 +4,6 @@
DCE120 = dce120_resource.o dce120_timing_generator.o \
dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \
dce120_mem_input.o dce120_hw_sequencer.o
AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120))
......
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/logger_interface.h"
#include "vega10/DC/dce_12_0_offset.h"
#include "vega10/DC/dce_12_0_sh_mask.h"
#include "vega10/soc15ip.h"
#include "dce120_ipp.h"
static const struct ipp_funcs funcs = {
.ipp_cursor_set_attributes = dce120_ipp_cursor_set_attributes,
.ipp_cursor_set_position = dce120_ipp_cursor_set_position,
.ipp_program_prescale = dce120_ipp_program_prescale,
.ipp_program_input_lut = dce120_ipp_program_input_lut,
.ipp_set_degamma = dce120_ipp_set_degamma,
};
bool dce120_ipp_construct(
struct dce110_ipp *ipp,
struct dc_context *ctx,
uint32_t inst,
const struct dce110_ipp_reg_offsets *offset)
{
if (!dce110_ipp_construct(ipp, ctx, inst, offset)) {
ASSERT_CRITICAL(false);
return false;
}
ipp->base.funcs = &funcs;
return true;
}
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_IPP_DCE120_H__
#define __DC_IPP_DCE120_H__
#include "ipp.h"
#include "../dce110/dce110_ipp.h"
bool dce120_ipp_construct(
struct dce110_ipp *ipp,
struct dc_context *ctx,
enum controller_id id,
const struct dce110_ipp_reg_offsets *offset);
/* CURSOR RELATED */
void dce120_ipp_cursor_set_position(
struct input_pixel_processor *ipp,
const struct dc_cursor_position *position,
const struct dc_cursor_mi_param *param);
void dce120_ipp_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attributes);
/* DEGAMMA RELATED */
bool dce120_ipp_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode);
void dce120_ipp_program_prescale(
struct input_pixel_processor *ipp,
struct ipp_prescale_params *params);
void dce120_ipp_program_input_lut(
struct input_pixel_processor *ipp,
const struct dc_gamma *gamma);
#endif /*__DC_IPP_DCE120_H__*/
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/logger_interface.h"
#include "include/fixed31_32.h"
#include "basics/conversion.h"
#include "vega10/DC/dce_12_0_offset.h"
#include "vega10/DC/dce_12_0_sh_mask.h"
#include "vega10/soc15ip.h"
#include "../dce110/dce110_ipp.h"
#define DCP_REG_UPDATE_N(reg_name, n, ...) \
generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__)
#define DCP_REG_SET_N(reg_name, n, ...) \
generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__)
#define DCP_REG_UPDATE(reg, field, val) \
DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \
DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \
DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
#define DCP_REG_SET(reg, field, val) \
DCP_REG_SET_N(reg, 1, FD(reg##__##field), val)
#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \
DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \
DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
bool dce120_ipp_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode)
{
struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||
mode == IPP_DEGAMMA_MODE_HW_sRGB);
DCP_REG_SET_3(
DCP0_DEGAMMA_CONTROL,
GRPH_DEGAMMA_MODE, degamma_type,
CURSOR_DEGAMMA_MODE, degamma_type,
CURSOR2_DEGAMMA_MODE, degamma_type);
return true;
}
void dce120_ipp_program_prescale(
struct input_pixel_processor *ipp,
struct ipp_prescale_params *params)
{
struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
/* set to bypass mode first before change */
DCP_REG_UPDATE(
DCP0_PRESCALE_GRPH_CONTROL,
GRPH_PRESCALE_BYPASS,
1);
DCP_REG_SET_2(
DCP0_PRESCALE_VALUES_GRPH_R,
GRPH_PRESCALE_SCALE_R, params->scale,
GRPH_PRESCALE_BIAS_R, params->bias);
DCP_REG_SET_2(
DCP0_PRESCALE_VALUES_GRPH_G,
GRPH_PRESCALE_SCALE_G, params->scale,
GRPH_PRESCALE_BIAS_G, params->bias);
DCP_REG_SET_2(
DCP0_PRESCALE_VALUES_GRPH_B,
GRPH_PRESCALE_SCALE_B, params->scale,
GRPH_PRESCALE_BIAS_B, params->bias);
if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL,
GRPH_PRESCALE_BYPASS, 0);
/* If prescale is in use, then legacy lut should be bypassed */
DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL,
GRPH_INPUT_GAMMA_MODE, 1);
}
}
static void dce120_helper_select_lut(struct dce110_ipp *ipp110)
{
/* enable all */
DCP_REG_SET(
DCP0_DC_LUT_WRITE_EN_MASK,
DC_LUT_WRITE_EN_MASK,
0x7);
/* 256 entry mode */
DCP_REG_UPDATE(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
/* LUT-256, unsigned, integer, new u0.12 format */
DCP_REG_SET_3(
DCP0_DC_LUT_CONTROL,
DC_LUT_DATA_R_FORMAT, 3,
DC_LUT_DATA_G_FORMAT, 3,
DC_LUT_DATA_B_FORMAT, 3);
/* start from index 0 */
DCP_REG_SET(
DCP0_DC_LUT_RW_INDEX,
DC_LUT_RW_INDEX,
0);
}
void dce120_ipp_program_input_lut(
struct input_pixel_processor *ipp,
const struct dc_gamma *gamma)
{
int i;
struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
/* power on LUT memory */
DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1);
dce120_helper_select_lut(ipp110);
for (i = 0; i < INPUT_LUT_ENTRIES; i++) {
DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]);
DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]);
DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]);
}
/* power off LUT memory */
DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0);
/* bypass prescale, enable legacy LUT */
DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
}
......@@ -40,7 +40,7 @@
#include "dce/dce_opp.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_clocks.h"
#include "dce120_ipp.h"
#include "dce/dce_ipp.h"
#include "dce110/dce110_mem_input.h"
#include "dce120/dce120_mem_input.h"
......@@ -174,6 +174,28 @@ static const struct dce_abm_mask abm_mask = {
ABM_MASK_SH_LIST_DCE110(_MASK)
};
#define ipp_regs(id)\
[id] = {\
IPP_COMMON_REG_LIST_DCE_BASE(id)\
}
static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs(0),
ipp_regs(1),
ipp_regs(2),
ipp_regs(3),
ipp_regs(4),
ipp_regs(5)
};
static const struct dce_ipp_shift ipp_shift = {
IPP_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
};
static const struct dce_ipp_mask ipp_mask = {
IPP_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
};
#define transform_regs(id)\
[id] = {\
XFM_COMMON_REG_LIST_DCE110(id)\
......@@ -354,27 +376,6 @@ struct output_pixel_processor *dce120_opp_create(
return NULL;
}
static const struct dce110_ipp_reg_offsets dce120_ipp_reg_offsets[] = {
{
.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
},
{
.dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL),
},
{
.dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL),
},
{
.dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL),
},
{
.dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL),
},
{
.dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL),
}
};
static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = {
{
.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
......@@ -498,7 +499,7 @@ static struct timing_generator *dce120_timing_generator_create(
static void dce120_ipp_destroy(struct input_pixel_processor **ipp)
{
dm_free(TO_DCE110_IPP(*ipp));
dm_free(TO_DCE_IPP(*ipp));
*ipp = NULL;
}
......@@ -622,21 +623,18 @@ struct link_encoder *dce120_link_encoder_create(
}
static struct input_pixel_processor *dce120_ipp_create(
struct dc_context *ctx,
uint32_t inst,
const struct dce110_ipp_reg_offsets *offset)
struct dc_context *ctx, uint32_t inst)
{
struct dce110_ipp *ipp = dm_alloc(sizeof(struct dce110_ipp));
struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
if (!ipp)
if (!ipp) {
BREAK_TO_DEBUGGER();
return NULL;
}
if (dce120_ipp_construct(ipp, ctx, inst, offset))
return &ipp->base;
BREAK_TO_DEBUGGER();
dm_free(ipp);
return NULL;
dce_ipp_construct(ipp, ctx, inst,
&ipp_regs[inst], &ipp_shift, &ipp_mask);
return &ipp->base;
}
static struct stream_encoder *dce120_stream_encoder_create(
......@@ -1025,8 +1023,7 @@ static bool construct(
goto controller_create_fail;
}
pool->base.ipps[i] = dce120_ipp_create(ctx, i,
&dce120_ipp_reg_offsets[i]);
pool->base.ipps[i] = dce120_ipp_create(ctx, i);
if (pool->base.ipps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
......
......@@ -26,6 +26,9 @@
#ifndef __DAL_HW_SHARED_H__
#define __DAL_HW_SHARED_H__
#include "os_types.h"
#include "fixed31_32.h"
/******************************************************************************
* Data types shared between different Virtual HW blocks
******************************************************************************/
......
/*
* Copyright 2015 Advanced Micro Devices, Inc.
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
......@@ -27,6 +27,7 @@
#define __DAL_IPP_H__
#include "hw_shared.h"
#include "dc_hw_types.h"
#define MAXTRIX_COEFFICIENTS_NUMBER 12
#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
......@@ -113,7 +114,7 @@ struct ipp_funcs {
const struct dc_gamma *gamma);
/*** DEGAMMA RELATED ***/
bool (*ipp_set_degamma)(
void (*ipp_set_degamma)(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode);
......
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