Commit d16605c9 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the big bulk of pin control changes for the v4.14 kernel.
  There are just a few bigger changes (new drivers mostly) and then a
  lot of small patches all over the place.

  Core changes:
   - Decision to wrap the sleep mode of the Spreadtrum and in the future
     others into a specially tagged state. The generic DT bindings and
     the new Spreadtrum driver conforms to this. Others should be moved
     over if possible.

  New drivers:
   - Spreadtrum SoCs especially the SC9860 SoC.
   - Storlink/Cortina Gemini 3512 and 3516 SoCs.

  New subdrivers:
   - Intel Denverton subdriver.
   - Intel Cannon Lake subdriver.
   - Intel Lewisburg subdriver.
   - Allwinner sunxi: R40 subdriver for A10.
   - Socionext uniphier PXs3 subdriver.
   - Rockchip RK3128 subdriver.
   - Renesas SH-PFC R8A77995 subdriver.

  Miscellaneous:
   - Qualcomm APQ8064 can handle general purpose clock muxing.
   - Mediatek MT7623 PCIe mux data fixed up.
   - Intel GPIO IRQs are disabled during suspend.
   - Several fixes and addtions to Renesas r8a7796.
   - Qualcomm SPMI GPIO supports dtest route and LV/MV subtype.
   - Input schmitt trigger support in Rockchip RV1108.
   - Aspeed G4 and G5 USB host/device pin control control added.
   - Qualcomm IPQ4019 has matured with a few missing pin groups and
     control bits put in place.
   - Lots of constification, this is the latest in cocinelle fixes"

* tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (147 commits)
  Revert "pinctrl: sunxi: Don't enforce bias disable (for now)"
  pinctrl: uniphier: fix members of rmii group for Pro4
  pinctrl: Delete an error message
  pinctrl: core: Delete an error message
  pinctrl: intel: Read back TX buffer state
  pinctrl: rockchip: Add rv1108 recalculated iomux support
  pinctrl: intel: Decrease indentation in intel_gpio_set()
  pinctrl: rza1: Remove suffix from gpiochip label
  pinctrl: qcom: spmi-gpio: Correct power_source range check
  pinctrl: freescale: make mxs_regs const
  pinctrl: aspeed: Rework strap register write logic for the AST2500
  pinctrl: rza1: off by one in rza1_parse_gpiochip()
  pinctrl: qcom: General Purpose clocks for apq8064
  pinctrl: sprd: Add Spreadtrum pin control driver
  dt-bindings: pinctrl: Add DT bindings for Spreadtrum SC9860
  pinctrl: Add sleep related state to indicate sleep related configs
  pinctrl: mediatek: update PCIe mux data for MT7623
  pinctrl: intel: Add Intel Lewisburg GPIO support
  pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support
  pinctrl: aspeed: Fix ast2500 strap register write logic
  ...
parents fe9e3138 ac059e2a
Cortina Systems Gemini pin controller
This pin controller is found in the Cortina Systems Gemini SoC family,
see further arm/gemini.txt. It is a purely group-based multiplexing pin
controller.
The pin controller node must be a subnode of the system controller node.
Required properties:
- compatible: "cortina,gemini-pinctrl"
Subnodes of the pin controller contain pin control multiplexing set-up.
Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
Example:
syscon {
compatible = "cortina,gemini-syscon";
...
pinctrl {
compatible = "cortina,gemini-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
<&vcontrol_default_pins>;
dram_default_pins: pinctrl-dram {
mux {
function = "dram";
groups = "dramgrp";
};
};
rtc_default_pins: pinctrl-rtc {
mux {
function = "rtc";
groups = "rtcgrp";
};
};
power_default_pins: pinctrl-power {
mux {
function = "power";
groups = "powergrp";
};
};
system_default_pins: pinctrl-system {
mux {
function = "system";
groups = "systemgrp";
};
};
(...)
uart_default_pins: pinctrl-uart {
mux {
function = "uart";
groups = "uartrxtxgrp";
};
};
};
};
* Freescale i.MX7ULP IOMUX Controller
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.
Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.
Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
binding.
=== Pin Controller Node ===
Required properties:
- compatible: "fsl,imx7ulp-iomuxc1"
- reg: Should contain the base physical address and size of the iomuxc
registers.
=== Pin Configuration Node ===
- pinmux: One integers array, represents a group of pins mux setting.
The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
a specific function.
NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
and config register as follows:
<mux_conf_reg input_reg mux_mode input_val>
Refer to imx7ulp-pinfunc.h in in device tree source folder for all
available imx7ulp PIN_FUNC_ID.
Optional Properties:
- drive-strength Integer. Controls Drive Strength
0: Standard
1: Hi Driver
- drive-push-pull Bool. Enable Pin Push-pull
- drive-open-drain Bool. Enable Pin Open-drian
- slew-rate: Integer. Controls Slew Rate
0: Standard
1: Slow
- bias-disable: Bool. Pull disabled
- bias-pull-down: Bool. Pull down on pin
- bias-pull-up: Bool. Pull up on pin
Examples:
#include "imx7ulp-pinfunc.h"
/* Pin Controller Node */
iomuxc1: iomuxc@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
pinmux = <
IMX7ULP_PAD_PTC3__LPUART4_RX
IMX7ULP_PAD_PTC2__LPUART4_TX
>;
bias-pull-up;
};
};
......@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
......@@ -86,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
VGAVS VPI24 VPO WDTRST1 WDTRST2
Examples
========
......
......@@ -268,6 +268,8 @@ output-enable - enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
sleep-hardware-state - indicate this is sleep related state which will be programmed
into the registers for the sleep state.
slew-rate - set the slew rate
For example:
......
......@@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
......
......@@ -46,7 +46,8 @@ Valid values for pins are:
gpio0-gpio89
Valid values for function are:
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
......
......@@ -50,7 +50,11 @@ Valid values for qcom,pins are:
Supports mux, bias and drive-strength
Valid values for qcom,function are:
gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1
Example:
......
......@@ -16,6 +16,7 @@ PMIC's from Qualcomm.
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8994-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
......@@ -85,6 +86,7 @@ to specify in a pin configuration subnode:
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994
- function:
Usage: required
......@@ -98,7 +100,10 @@ to specify in a pin configuration subnode:
"dtest1",
"dtest2",
"dtest3",
"dtest4"
"dtest4",
And following values are supported by LV/MV GPIO subtypes:
"func3",
"func4"
- bias-disable:
Usage: optional
......@@ -183,6 +188,25 @@ to specify in a pin configuration subnode:
Value type: <none>
Definition: The specified pins are configured in open-source mode.
- qcom,analog-pass:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in analog-pass-through mode.
- qcom,atest:
Usage: optional
Value type: <u32>
Definition: Selects ATEST rail to route to GPIO when it's configured
in analog-pass-through mode.
Valid values are 1-4 corresponding to ATEST1 to ATEST4.
- qcom,dtest-buffer:
Usage: optional
Value type: <u32>
Definition: Selects DTEST rail to route to GPIO when it's configured
as digital input.
Valid values are 1-4 corresponding to DTEST1 to DTEST4.
Example:
pm8921_gpio: gpio@150 {
......
......@@ -24,6 +24,7 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
......
......@@ -24,6 +24,7 @@ Required properties for iomux controller:
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
"rockchip,rk3128-pinctrl": for Rockchip RK3128
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288
......
* Spreadtrum Pin Controller
The Spreadtrum pin controller are organized in 3 blocks (types).
The first block comprises some global control registers, and each
register contains several bit fields with one bit or several bits
to configure for some global common configuration, such as domain
pad driving level, system control select and so on ("domain pad
driving level": One pin can output 3.0v or 1.8v, depending on the
related domain pad driving selection, if the related domain pad
slect 3.0v, then the pin can output 3.0v. "system control" is used
to choose one function (like: UART0) for which system, since we
have several systems (AP/CP/CM4) on one SoC.).
There are too much various configuration that we can not list all
of them, so we can not make every Spreadtrum-special configuration
as one generic configuration, and maybe it will add more strange
global configuration in future. Then we add one "sprd,control" to
set these various global control configuration, and we need use
magic number for this property.
Moreover we recognise every fields comprising one bit or several
bits in one global control register as one pin, thus we should
record every pin's bit offset, bit width and register offset to
configure this field (pin).
The second block comprises some common registers which have unified
register definition, and each register described one pin is used
to configure the pin sleep mode, function select and sleep related
configuration.
Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
related configuration are:
- input-enable
- input-disable
- output-high
- output-low
- bias-pull-up
- bias-pull-down
In some situation we need set the pin sleep mode and pin sleep related
configuration, to set the pin sleep related configuration automatically
by hardware when the system specified by sleep mode goes into deep
sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
and set the pin sleep related configuration as "input-enable", which
means when PUBCP system goes into deep sleep mode, this pin will be set
input enable automatically.
Moreover we can not use the "sleep" state, since some systems (like:
PUBCP system) do not run linux kernel OS (only AP system run linux
kernel on SC9860 platform), then we can not select "sleep" state
when the PUBCP system goes into deep sleep mode. Thus we introduce
"sprd,sleep-mode" property to set pin sleep mode.
The last block comprises some misc registers which also have unified
register definition, and each register described one pin is used to
configure drive strength, pull up/down and so on. Especially for pull
up, we have two kind pull up resistor: 20K and 4.7K.
Required properties for Spreadtrum pin controller:
- compatible: "sprd,<soc>-pinctrl"
Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
- reg: The register address of pin controller device.
- pins : An array of pin names.
Optional properties:
- function: Specified the function name.
- drive-strength: Drive strength in mA.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Sleep mode selection.
Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.
* Spreadtrum SC9860 Pin Controller
Please refer to sprd,pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: Must be "sprd,sc9860-pinctrl".
- reg: The register address of pin controller device.
- pins : An array of strings, each string containing the name of a pin.
Optional properties:
- function: A string containing the name of the function, values must be
one of: "func1", "func2", "func3" and "func4".
- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
is 20K and 4700 for pull-up resistor is 4.7K.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Choose the pin sleep mode, and supported values are:
AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP.
Pin sleep mode definition:
enum pin_sleep_mode {
AP_SLEEP = BIT(0),
PUBCP_SLEEP = BIT(1),
TGLDSP_SLEEP = BIT(2),
AGDSP_SLEEP = BIT(3),
};
Example:
pin_controller: pinctrl@402a0000 {
compatible = "sprd,sc9860-pinctrl";
reg = <0x402a0000 0x10000>;
grp1: sd0 {
pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
sprd,control = <0x1>;
};
grp2: rfctl_33 {
pins = "SC9860_RFCTL33";
function = "func2";
sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>;
grp2_sleep_mode: rfctl_33_sleep {
pins = "SC9860_RFCTL33";
sleep-hardware-state;
output-low;
}
};
grp3: rfctl_misc_20 {
pins = "SC9860_RFCTL20_MISC";
drive-strength = <10>;
bias-pull-up = <4700>;
grp3_sleep_mode: rfctl_misc_sleep {
pins = "SC9860_RFCTL20_MISC";
sleep-hardware-state;
bias-pull-up;
}
};
};
......@@ -1282,10 +1282,15 @@ S: Maintained
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://github.com/ulli-kroll/linux.git
S: Maintained
F: Documentation/devicetree/bindings/arm/gemini.txt
F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
F: arch/arm/mach-gemini/
F: drivers/pinctrl/pinctrl-gemini.c
F: drivers/rtc/rtc-ftrtc010.c
ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
......
This diff is collapsed.
......@@ -146,6 +146,13 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
config PINCTRL_GEMINI
bool
depends on ARCH_GEMINI
default ARCH_GEMINI
select PINMUX
select MFD_SYSCON
config PINCTRL_MCP23S08
tristate "Microchip MCP23xxx I/O expander"
depends on SPI_MASTER || I2C
......@@ -343,6 +350,7 @@ source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/tegra/Kconfig"
......
......@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
......@@ -55,6 +56,7 @@ obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-y += ti/
......
......@@ -1006,15 +1006,23 @@ SS_PIN_DECL(H3, GPIOQ5, SDA14);
FUNC_GROUP_DECL(I2C14, H4, H3);
#define DASH9028_DESC SIG_DESC_SET(SCU90, 28)
/*
* There are several opportunities to document USB port 4 in the datasheet, but
* it is only mentioned in one location. Particularly, the Multi-function Pins
* Mapping and Control table in the datasheet elides the signal names,
* suggesting that port 4 may not actually be functional. As such we define the
* signal names and control bit, but don't export the capability's function or
* group.
*/
#define USB11H3_DESC SIG_DESC_SET(SCU90, 28)
#define H2 134
SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC);
SS_PIN_DECL(H2, GPIOQ6, DASHH2);
SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC);
SS_PIN_DECL(H2, GPIOQ6, USB11HDP3);
#define H1 135
SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC);
SS_PIN_DECL(H1, GPIOQ7, DASHH1);
SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC);
SS_PIN_DECL(H1, GPIOQ7, USB11HDN3);
#define V20 136
SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24));
......@@ -1706,10 +1714,42 @@ FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
P20, P21, P22, M19, M20, M21, M22, L18, L19);
#define USB11H2_DESC SIG_DESC_SET(SCU90, 3)
#define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0)
#define K4 220
SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC);
MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1));
#define K3 221
SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC);
MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1));
FUNC_GROUP_DECL(USB11H2, K4, K3);
FUNC_GROUP_DECL(USB11D1, K4, K3);
#define USB2H1_DESC SIG_DESC_SET(SCU90, 29)
#define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0)
#define AB21 222
SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC);
MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1));
#define AB20 223
SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC);
MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1));
FUNC_GROUP_DECL(USB2H1, AB21, AB20);
FUNC_GROUP_DECL(USB2D1, AB21, AB20);
/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
* pins becomes 220.
* pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
*/
#define ASPEED_G4_NR_PINS 220
#define ASPEED_G4_NR_PINS 224
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
......@@ -1749,6 +1789,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(AB6),
ASPEED_PINCTRL_PIN(AB7),
ASPEED_PINCTRL_PIN(AB20),
ASPEED_PINCTRL_PIN(AB21),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
......@@ -1848,6 +1890,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(J5),
ASPEED_PINCTRL_PIN(K18),
ASPEED_PINCTRL_PIN(K20),
ASPEED_PINCTRL_PIN(K3),
ASPEED_PINCTRL_PIN(K4),
ASPEED_PINCTRL_PIN(K5),
ASPEED_PINCTRL_PIN(L1),
ASPEED_PINCTRL_PIN(L18),
......@@ -2070,6 +2114,10 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(USB11D1),
ASPEED_PINCTRL_GROUP(USB11H2),
ASPEED_PINCTRL_GROUP(USB2D1),
ASPEED_PINCTRL_GROUP(USB2H1),
ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
ASPEED_PINCTRL_GROUP(VGAHS),
......@@ -2221,6 +2269,10 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
ASPEED_PINCTRL_FUNC(USB11D1),
ASPEED_PINCTRL_FUNC(USB11H2),
ASPEED_PINCTRL_FUNC(USB2D1),
ASPEED_PINCTRL_FUNC(USB2H1),
ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
ASPEED_PINCTRL_FUNC(VGAHS),
......@@ -2349,7 +2401,7 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
};
static struct pinmux_ops aspeed_g4_pinmux_ops = {
static const struct pinmux_ops aspeed_g4_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
......@@ -2358,7 +2410,7 @@ static struct pinmux_ops aspeed_g4_pinmux_ops = {
.strict = true,
};
static struct pinctrl_ops aspeed_g4_pinctrl_ops = {
static const struct pinctrl_ops aspeed_g4_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
......
......@@ -25,7 +25,7 @@
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
#define ASPEED_G5_NR_PINS 232
#define ASPEED_G5_NR_PINS 236
#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
......@@ -1724,6 +1724,48 @@ FUNC_GROUP_DECL(LPCRST, G22);
FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
#define A7 232
SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP));
#define A8 233
SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN));
FUNC_GROUP_DECL(USB2AH, A7, A8);
FUNC_GROUP_DECL(USB2AD, A7, A8);
#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
#define B6 234
SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH),
SIG_EXPR_PTR(USB2BHDP2, USB2BH));
MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP),
SIG_EXPR_LIST_PTR(USB2BHDP));
#define A6 235
SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH),
SIG_EXPR_PTR(USB2BHDN2, USB2BH));
MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN),
SIG_EXPR_LIST_PTR(USB2BHDN));
FUNC_GROUP_DECL(USB11BHID, B6, A6);
FUNC_GROUP_DECL(USB2BD, B6, A6);
FUNC_GROUP_DECL(USB2BH, B6, A6);
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
......@@ -1743,6 +1785,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
ASPEED_PINCTRL_PIN(A9),
ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA19),
......@@ -1777,6 +1822,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
ASPEED_PINCTRL_PIN(C11),
......@@ -2111,6 +2157,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(USB11BHID),