1. 08 Jun, 2017 2 commits
  2. 07 Jun, 2017 24 commits
    • Neil Armstrong's avatar
      drm/meson: Fix driver bind when only CVBS is available · 8604889f
      Neil Armstrong authored
      While introducing HDMI support, component matching on connectors node
      were bypassed since no driver would actually bind on the DT node.
      But when only a CVBS connector is present, only a single node is found
      in the graph, but ignored and a NULL match table is given to the
      component code.
      
      This code permits bypassing the components framework by binding directly
      the DRM driver when no components needs to be loaded.
      
      Fixes: a41e82e6 ("drm/meson: Add support for components")
      Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
      Link: http://patchwork.freedesktop.org/patch/msgid/1496067352-8733-1-git-send-email-narmstrong@baylibre.com
      8604889f
    • Ville Syrjälä's avatar
      drm/i915: Fix 90/270 rotated coordinates for FBC · 1065467e
      Ville Syrjälä authored
      The clipped src coordinates have already been rotated by 270 degrees for
      when the plane rotation is 90/270 degrees, hence the FBC code should no
      longer swap the width and height.
      
      Cc: stable@vger.kernel.org
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Fixes: b63a16f6 ("drm/i915: Compute display surface offset in the plane check hook for SKL+")
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170331180056.14086-4-ville.syrjala@linux.intel.comReviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      (cherry picked from commit 73714c05)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      1065467e
    • Ville Syrjälä's avatar
      drm/i915: Restore has_fbc=1 for ILK-M · 27fe407c
      Ville Syrjälä authored
      Restore the lost has_fbc flag for mobile ILK.
      
      Cc: Carlos Santa <carlos.santa@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Fixes: a1323380 ("drm/i915: Introduce GEN5_FEATURES for device info")
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170606133229.12439-1-ville.syrjala@linux.intel.comReviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      (cherry picked from commit c2d1a0ce)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      27fe407c
    • Ville Syrjälä's avatar
      drm/i915: Workaround VLV/CHV DSI scanline counter hardware fail · 8f4d3809
      Ville Syrjälä authored
      The scanline counter is bonkers on VLV/CHV DSI. The scanline counter
      increment is not lined up with the start of vblank like it is on
      every other platform and output type. This causes problems for
      both the vblank timestamping and atomic update vblank evasion.
      
      On my FFRD8 machine at least, the scanline counter increment
      happens about 1/3 of a scanline ahead of the start of vblank (which
      is where all register latching happens still). That means we can't
      trust the scanline counter to tell us whether we're in vblank or not
      while we're on that particular line. In order to keep vblank
      timestamping in working condition when called from the vblank irq,
      we'll leave scanline_offset at one, which means that the entire
      line containing the start of vblank is considered to be inside
      the vblank.
      
      For the vblank evasion we'll need to consider that entire line
      to be bad, since we can't tell whether the registers already
      got latched or not. And we can't actually use the start of vblank
      interrupt to get us past that line as the interrupt would fire
      too soon, and then we'd up waiting for the next start of vblank
      instead. One way around that would using the frame start
      interrupt instead since that wouldn't fire until the next
      scanline, but that would require some bigger changes in the
      interrupt code. So for simplicity we'll just poll until we get
      past the bad line.
      
      v2: Adjust the comments a bit
      
      Cc: stable@vger.kernel.org
      Cc: Jonas Aaberg <cja@gmx.net>
      Tested-by: default avatarJonas Aaberg <cja@gmx.net>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99086Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20161215174734.28779-1-ville.syrjala@linux.intel.comTested-by: default avatarMika Kahola <mika.kahola@intel.com>
      Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
      (cherry picked from commit ec1b4ee2)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      8f4d3809
    • Chris Wilson's avatar
      drm/i915: Fix logical inversion for gen4 quirking · 5857dbfa
      Chris Wilson authored
      The assertion that we want to make before disabling the pin of the pages
      for the unknown swizzling quirk is that the quirk is indeed active, and
      that the quirk is disabled before we do apply it to the pages.
      
      Fixes: 2c3a3f44 ("drm/i915: Fix pages pin counting around swizzle quirk")
      Fixes: 957870f9 ("drm/i915: Split out i915_gem_object_set_tiling()")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170521124014.27678-1-chris@chris-wilson.co.uk
      Reviewed-bhy: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      (cherry picked from commit 20bb3771)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      5857dbfa
    • Chris Wilson's avatar
      drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally · d90c9890
      Chris Wilson authored
      Commit 7c3f86b6 ("drm/i915: Invalidate the guc ggtt TLB upon
      insertion") added the restoration of the invalidation routine after the
      GuC was disabled, but missed that the GuC was unconditionally disabled
      when not used. This then overwrites the invalidate routine for the older
      chipsets, causing havoc and breaking resume as the most obvious victim.
      
      We place the guard inside i915_ggtt_disable_guc() to be backport
      friendly (the bug was introduced into v4.11) but it would be preferred
      to be in more control over when this was guard (i.e. do not try and
      teardown the data structures before we have enabled them). That should
      be true with the reorganisation of the guc loaders.
      Reported-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Fixes: 7c3f86b6 ("drm/i915: Invalidate the guc ggtt TLB upon insertion")
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Oscar Mateo <oscar.mateo@intel.com>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
      Cc: <stable@vger.kernel.org> # v4.11+
      Link: http://patchwork.freedesktop.org/patch/msgid/20170531190514.3691-1-chris@chris-wilson.co.ukReviewed-by: default avatarMichel Thierry <michel.thierry@intel.com>
      (cherry picked from commit cb60606d)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      d90c9890
    • Maarten Lankhorst's avatar
      drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2. · 4e3aed84
      Maarten Lankhorst authored
      On some systems there can be a race condition in which no crtc state is
      added to the first atomic commit. This results in all crtc's having a
      null DDB allocation, causing a FIFO underrun on any update until the
      first modeset.
      
      Changes since v1:
      - Do not take the connection_mutex, this is already done below.
      Reported-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Inspired-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
      Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Fixes: 98d39494 ("drm/i915/gen9: Compute DDB allocation at atomic
      check time (v4)")
      Cc: <stable@vger.kernel.org> # v4.8+
      Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170531154236.27180-1-maarten.lankhorst@linux.intel.comReviewed-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
      Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
      
      (cherry picked from commit 367d73d2)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      4e3aed84
    • Imre Deak's avatar
      drm/i915: Prevent the system suspend complete optimization · 6ab92afc
      Imre Deak authored
      Since
      
      commit bac2a909
      Author: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
      Date:   Wed Jan 21 02:17:42 2015 +0100
      
          PCI / PM: Avoid resuming PCI devices during system suspend
      
      PCI devices will default to allowing the system suspend complete
      optimization where devices are not woken up during system suspend if
      they were already runtime suspended. This however breaks the i915/HDA
      drivers for two reasons:
      
      - The i915 driver has system suspend specific steps that it needs to
        run, that bring the device to a different state than its runtime
        suspended state.
      
      - The HDA driver's suspend handler requires power that it will request
        from the i915 driver's power domain handler. This in turn requires the
        i915 driver to runtime resume itself, but this won't be possible if the
        suspend complete optimization is in effect: in this case the i915
        runtime PM is disabled and trying to get an RPM reference returns
        -EACCESS.
      
      Solve this by requiring the PCI/PM core to resume the device during
      system suspend which in effect disables the suspend complete optimization.
      
      Regardless of the above commit the optimization stayed disabled for DRM
      devices until
      
      commit d14d2a84
      Author: Lukas Wunner <lukas@wunner.de>
      Date:   Wed Jun 8 12:49:29 2016 +0200
      
          drm: Remove dev_pm_ops from drm_class
      
      so this patch is in practice a fix for this commit. Another reason for
      the bug staying hidden for so long is that the optimization for a device
      is disabled if it's disabled for any of its children devices. i915 may
      have a backlight device as its child which doesn't support runtime PM
      and so doesn't allow the optimization either.  So if this backlight
      device got registered the bug stayed hidden.
      
      Credits to Marta, Tomi and David who enabled pstore logging,
      that caught one instance of this issue across a suspend/
      resume-to-ram and Ville who rememberd that the optimization was enabled
      for some devices at one point.
      
      The first WARN triggered by the problem:
      
      [ 6250.746445] WARNING: CPU: 2 PID: 17384 at drivers/gpu/drm/i915/intel_runtime_pm.c:2846 intel_runtime_pm_get+0x6b/0xd0 [i915]
      [ 6250.746448] pm_runtime_get_sync() failed: -13
      [ 6250.746451] Modules linked in: snd_hda_intel i915 vgem snd_hda_codec_hdmi x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul
      snd_hda_codec_realtek snd_hda_codec_generic ghash_clmulni_intel e1000e snd_hda_codec snd_hwdep snd_hda_core ptp mei_me pps_core snd_pcm lpc_ich mei prime_
      numbers i2c_hid i2c_designware_platform i2c_designware_core [last unloaded: i915]
      [ 6250.746512] CPU: 2 PID: 17384 Comm: kworker/u8:0 Tainted: G     U  W       4.11.0-rc5-CI-CI_DRM_334+ #1
      [ 6250.746515] Hardware name:                  /NUC5i5RYB, BIOS RYBDWi35.86A.0362.2017.0118.0940 01/18/2017
      [ 6250.746521] Workqueue: events_unbound async_run_entry_fn
      [ 6250.746525] Call Trace:
      [ 6250.746530]  dump_stack+0x67/0x92
      [ 6250.746536]  __warn+0xc6/0xe0
      [ 6250.746542]  ? pci_restore_standard_config+0x40/0x40
      [ 6250.746546]  warn_slowpath_fmt+0x46/0x50
      [ 6250.746553]  ? __pm_runtime_resume+0x56/0x80
      [ 6250.746584]  intel_runtime_pm_get+0x6b/0xd0 [i915]
      [ 6250.746610]  intel_display_power_get+0x1b/0x40 [i915]
      [ 6250.746646]  i915_audio_component_get_power+0x15/0x20 [i915]
      [ 6250.746654]  snd_hdac_display_power+0xc8/0x110 [snd_hda_core]
      [ 6250.746661]  azx_runtime_resume+0x218/0x280 [snd_hda_intel]
      [ 6250.746667]  pci_pm_runtime_resume+0x76/0xa0
      [ 6250.746672]  __rpm_callback+0xb4/0x1f0
      [ 6250.746677]  ? pci_restore_standard_config+0x40/0x40
      [ 6250.746682]  rpm_callback+0x1f/0x80
      [ 6250.746686]  ? pci_restore_standard_config+0x40/0x40
      [ 6250.746690]  rpm_resume+0x4ba/0x740
      [ 6250.746698]  __pm_runtime_resume+0x49/0x80
      [ 6250.746703]  pci_pm_suspend+0x57/0x140
      [ 6250.746709]  dpm_run_callback+0x6f/0x330
      [ 6250.746713]  ? pci_pm_freeze+0xe0/0xe0
      [ 6250.746718]  __device_suspend+0xf9/0x370
      [ 6250.746724]  ? dpm_watchdog_set+0x60/0x60
      [ 6250.746730]  async_suspend+0x1a/0x90
      [ 6250.746735]  async_run_entry_fn+0x34/0x160
      [ 6250.746741]  process_one_work+0x1f2/0x6d0
      [ 6250.746749]  worker_thread+0x49/0x4a0
      [ 6250.746755]  kthread+0x107/0x140
      [ 6250.746759]  ? process_one_work+0x6d0/0x6d0
      [ 6250.746763]  ? kthread_create_on_node+0x40/0x40
      [ 6250.746768]  ret_from_fork+0x2e/0x40
      [ 6250.746778] ---[ end trace 102a62fd2160f5e6 ]---
      
      v2:
      - Use the new pci_dev->needs_resume flag, to avoid any overhead during
        the ->pm_prepare hook. (Rafael)
      
      v3:
      - Update commit message to reference the actual regressing commit.
        (Lukas)
      
      v4:
      - Rebase on v4 of patch 1/2.
      
      Fixes: d14d2a84 ("drm: Remove dev_pm_ops from drm_class")
      References: https://bugs.freedesktop.org/show_bug.cgi?id=100378
      References: https://bugs.freedesktop.org/show_bug.cgi?id=100770
      Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
      Cc: Marta Lofstedt <marta.lofstedt@intel.com>
      Cc: David Weinehall <david.weinehall@linux.intel.com>
      Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Takashi Iwai <tiwai@suse.de>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Lukas Wunner <lukas@wunner.de>
      Cc: linux-pci@vger.kernel.org
      Cc: <stable@vger.kernel.org> # v4.10.x: 4d071c32 - PCI/PM: Add needs_resume flag
      Cc: <stable@vger.kernel.org> # v4.10.x
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Reported-and-tested-by: default avatarMarta Lofstedt <marta.lofstedt@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1493726649-32094-2-git-send-email-imre.deak@intel.com
      (cherry picked from commit adfdf85d)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      6ab92afc
    • Nagaraju, Vathsala's avatar
      drm/i915/psr: disable psr2 for resolution greater than 32X20 · bd709898
      Nagaraju, Vathsala authored
      psr1 is also disabled for panel resolution  greater than 32X20.
      Added psr2 check to disable only for psr2 panels having resolution
      greater than 32X20.
      
      issue was introduced by
      commit-id : "acf45d11"
      commit message: "PSR2 is restricted to work with panel resolutions
      upto 3200x2000, move the check to intel_psr_match_conditions and fully
      block psr."
      
      v2: (Rodrigo)
         Add previous commit details which introduced the issue
      
      Fixes: acf45d11 ("drm/i915/psr: disable psr2 for resolution greater than 32X20")
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: Jim Bride <jim.bride@linux.intel.com>
      Cc: Yaroslav Shabalin <yaroslav.shabalin@gmail.com>
      Reported-by: default avatarYaroslav Shabalin <yaroslav.shabalin@gmail.com>
      Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: default avatarvathsala nagaraju <vathsala.nagaraju@intel.com>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/49935bdff896ee3140bed471012b9f9110a863a4.1495729964.git.vathsala.nagaraju@intel.com
      (cherry picked from commit bef8c056)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      bd709898
    • Chris Wilson's avatar
      drm/i915: Hold a wakeref for probing the ring registers · d9533f19
      Chris Wilson authored
      Allow intel_engine_is_idle() to be called outside of the GT wakeref by
      acquiring the device runtime pm for ourselves. This allows the function
      to act as check after we assume the engine is idle and we release the GT
      wakeref held whilst we have requests. At the moment, we do not call it
      outside of an awake context but taking the wakeref as required makes it
      more convenient to use for quick debugging in future.
      
      [ 2613.401647] RPM wakelock ref not held during HW access
      [ 2613.401684] ------------[ cut here ]------------
      [ 2613.401720] WARNING: CPU: 5 PID: 7739 at drivers/gpu/drm/i915/intel_drv.h:1787 gen6_read32+0x21f/0x2b0 [i915]
      [ 2613.401731] Modules linked in: snd_hda_intel i915 vgem snd_hda_codec_hdmi x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_realtek coretemp snd_hda_codec_generic crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm r8169 mii mei_me lpc_ich mei prime_numbers [last unloaded: i915]
      [ 2613.401823] CPU: 5 PID: 7739 Comm: drv_missed_irq Tainted: G     U          4.12.0-rc2-CI-CI_DRM_421+ #1
      [ 2613.401825] Hardware name: MSI MS-7924/Z97M-G43(MS-7924), BIOS V1.12 02/15/2016
      [ 2613.401840] task: ffff880409e3a740 task.stack: ffffc900084dc000
      [ 2613.401861] RIP: 0010:gen6_read32+0x21f/0x2b0 [i915]
      [ 2613.401863] RSP: 0018:ffffc900084dfce8 EFLAGS: 00010292
      [ 2613.401869] RAX: 000000000000002a RBX: ffff8804016a8000 RCX: 0000000000000006
      [ 2613.401871] RDX: 0000000000000006 RSI: ffffffff81cbf2d9 RDI: ffffffff81c9e3a7
      [ 2613.401874] RBP: ffffc900084dfd18 R08: ffff880409e3afc8 R09: 0000000000000000
      [ 2613.401877] R10: 000000008a1c483f R11: 0000000000000000 R12: 000000000000209c
      [ 2613.401879] R13: 0000000000000001 R14: ffff8804016a8000 R15: ffff8804016ac150
      [ 2613.401882] FS:  00007f39ef3dd8c0(0000) GS:ffff88041fb40000(0000) knlGS:0000000000000000
      [ 2613.401885] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [ 2613.401887] CR2: 00000000023717c8 CR3: 00000002e7b34000 CR4: 00000000001406e0
      [ 2613.401889] Call Trace:
      [ 2613.401912]  intel_engine_is_idle+0x76/0x90 [i915]
      [ 2613.401931]  i915_gem_wait_for_idle+0xe6/0x1e0 [i915]
      [ 2613.401951]  fault_irq_set+0x40/0x90 [i915]
      [ 2613.401970]  i915_ring_test_irq_set+0x42/0x50 [i915]
      [ 2613.401976]  simple_attr_write+0xc7/0xe0
      [ 2613.401981]  full_proxy_write+0x4f/0x70
      [ 2613.401987]  __vfs_write+0x23/0x120
      [ 2613.401992]  ? rcu_read_lock_sched_held+0x75/0x80
      [ 2613.401996]  ? rcu_sync_lockdep_assert+0x2a/0x50
      [ 2613.401999]  ? __sb_start_write+0xfa/0x1f0
      [ 2613.402004]  vfs_write+0xc5/0x1d0
      [ 2613.402008]  ? trace_hardirqs_on_caller+0xe7/0x1c0
      [ 2613.402013]  SyS_write+0x44/0xb0
      [ 2613.402020]  entry_SYSCALL_64_fastpath+0x1c/0xb1
      [ 2613.402022] RIP: 0033:0x7f39eded6670
      [ 2613.402025] RSP: 002b:00007fffdcdcb1a8 EFLAGS: 00000246 ORIG_RAX: 0000000000000001
      [ 2613.402030] RAX: ffffffffffffffda RBX: ffffffff81470203 RCX: 00007f39eded6670
      [ 2613.402033] RDX: 0000000000000001 RSI: 000000000041bc33 RDI: 0000000000000006
      [ 2613.402036] RBP: ffffc900084dff88 R08: 00007f39ef3dd8c0 R09: 0000000000000001
      [ 2613.402038] R10: 0000000000000000 R11: 0000000000000246 R12: 000000000041bc33
      [ 2613.402041] R13: 0000000000000006 R14: 0000000000000000 R15: 0000000000000000
      [ 2613.402046]  ? __this_cpu_preempt_check+0x13/0x20
      [ 2613.402052] Code: 01 9b fa e0 0f ff e9 28 fe ff ff 80 3d 6a dd 0e 00 00 0f 85 29 fe ff ff 48 c7 c7 48 19 29 a0 c6 05 56 dd 0e 00 01 e8 da 9a fa e0 <0f> ff e9 0f fe ff ff b9 01 00 00 00 ba 01 00 00 00 44 89 e6 48
      [ 2613.402199] ---[ end trace 31f0cfa93ab632bf ]---
      
      Fixes: 5400367a ("drm/i915: Ensure the engine is idle before manually changing HWS")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170530121334.17364-2-chris@chris-wilson.co.ukReviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      (cherry picked from commit a091d4ee)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      d9533f19
    • Chris Wilson's avatar
      drm/i915: Short-circuit i915_gem_wait_for_idle() if already idle · e0da1963
      Chris Wilson authored
      If the device is asleep (no GT wakeref), we know the GPU is already idle.
      If we add an early return, we can avoid touching registers and checking
      hw state outside of the assumed GT wakelock. This prevents causing such
      errors whilst debugging:
      
      [ 2613.401647] RPM wakelock ref not held during HW access
      [ 2613.401684] ------------[ cut here ]------------
      [ 2613.401720] WARNING: CPU: 5 PID: 7739 at drivers/gpu/drm/i915/intel_drv.h:1787 gen6_read32+0x21f/0x2b0 [i915]
      [ 2613.401731] Modules linked in: snd_hda_intel i915 vgem snd_hda_codec_hdmi x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_realtek coretemp snd_hda_codec_generic crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm r8169 mii mei_me lpc_ich mei prime_numbers [last unloaded: i915]
      [ 2613.401823] CPU: 5 PID: 7739 Comm: drv_missed_irq Tainted: G     U          4.12.0-rc2-CI-CI_DRM_421+ #1
      [ 2613.401825] Hardware name: MSI MS-7924/Z97M-G43(MS-7924), BIOS V1.12 02/15/2016
      [ 2613.401840] task: ffff880409e3a740 task.stack: ffffc900084dc000
      [ 2613.401861] RIP: 0010:gen6_read32+0x21f/0x2b0 [i915]
      [ 2613.401863] RSP: 0018:ffffc900084dfce8 EFLAGS: 00010292
      [ 2613.401869] RAX: 000000000000002a RBX: ffff8804016a8000 RCX: 0000000000000006
      [ 2613.401871] RDX: 0000000000000006 RSI: ffffffff81cbf2d9 RDI: ffffffff81c9e3a7
      [ 2613.401874] RBP: ffffc900084dfd18 R08: ffff880409e3afc8 R09: 0000000000000000
      [ 2613.401877] R10: 000000008a1c483f R11: 0000000000000000 R12: 000000000000209c
      [ 2613.401879] R13: 0000000000000001 R14: ffff8804016a8000 R15: ffff8804016ac150
      [ 2613.401882] FS:  00007f39ef3dd8c0(0000) GS:ffff88041fb40000(0000) knlGS:0000000000000000
      [ 2613.401885] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [ 2613.401887] CR2: 00000000023717c8 CR3: 00000002e7b34000 CR4: 00000000001406e0
      [ 2613.401889] Call Trace:
      [ 2613.401912]  intel_engine_is_idle+0x76/0x90 [i915]
      [ 2613.401931]  i915_gem_wait_for_idle+0xe6/0x1e0 [i915]
      [ 2613.401951]  fault_irq_set+0x40/0x90 [i915]
      [ 2613.401970]  i915_ring_test_irq_set+0x42/0x50 [i915]
      [ 2613.401976]  simple_attr_write+0xc7/0xe0
      [ 2613.401981]  full_proxy_write+0x4f/0x70
      [ 2613.401987]  __vfs_write+0x23/0x120
      [ 2613.401992]  ? rcu_read_lock_sched_held+0x75/0x80
      [ 2613.401996]  ? rcu_sync_lockdep_assert+0x2a/0x50
      [ 2613.401999]  ? __sb_start_write+0xfa/0x1f0
      [ 2613.402004]  vfs_write+0xc5/0x1d0
      [ 2613.402008]  ? trace_hardirqs_on_caller+0xe7/0x1c0
      [ 2613.402013]  SyS_write+0x44/0xb0
      [ 2613.402020]  entry_SYSCALL_64_fastpath+0x1c/0xb1
      [ 2613.402022] RIP: 0033:0x7f39eded6670
      [ 2613.402025] RSP: 002b:00007fffdcdcb1a8 EFLAGS: 00000246 ORIG_RAX: 0000000000000001
      [ 2613.402030] RAX: ffffffffffffffda RBX: ffffffff81470203 RCX: 00007f39eded6670
      [ 2613.402033] RDX: 0000000000000001 RSI: 000000000041bc33 RDI: 0000000000000006
      [ 2613.402036] RBP: ffffc900084dff88 R08: 00007f39ef3dd8c0 R09: 0000000000000001
      [ 2613.402038] R10: 0000000000000000 R11: 0000000000000246 R12: 000000000041bc33
      [ 2613.402041] R13: 0000000000000006 R14: 0000000000000000 R15: 0000000000000000
      [ 2613.402046]  ? __this_cpu_preempt_check+0x13/0x20
      [ 2613.402052] Code: 01 9b fa e0 0f ff e9 28 fe ff ff 80 3d 6a dd 0e 00 00 0f 85 29 fe ff ff 48 c7 c7 48 19 29 a0 c6 05 56 dd 0e 00 01 e8 da 9a fa e0 <0f> ff e9 0f fe ff ff b9 01 00 00 00 ba 01 00 00 00 44 89 e6 48
      [ 2613.402199] ---[ end trace 31f0cfa93ab632bf ]---
      
      Fixes: 25112b64 ("drm/i915: Wait for all engines to be idle as part of i915_gem_wait_for_idle()")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170530121334.17364-1-chris@chris-wilson.co.ukReviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      (cherry picked from commit 863e9fde)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      e0da1963
    • Kai Chen's avatar
      drm/i915: Disable decoupled MMIO · 4c4c5655
      Kai Chen authored
      The decoupled MMIO feature doesn't work as intended by HW team. Enabling
      it with forcewake will only make debugging efforts more difficult, so
      let's disable it.
      
      Fixes: 85ee17eb ("drm/i915/bxt: Broxton decoupled MMIO")
      Cc: Zhe Wang <zhe1.wang@intel.com>
      Cc: Praveen Paneri <praveen.paneri@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      Cc: Jani Nikula <jani.nikula@linux.intel.com>
      Cc: intel-gfx@lists.freedesktop.org
      Cc: <stable@vger.kernel.org> # v4.10+
      Signed-off-by: default avatarKai Chen <kai.chen@intel.com>
      Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170523215812.18328-2-kai.chen@intel.com
      (cherry picked from commit 0051c10a)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      4c4c5655
    • Michal Wajdeczko's avatar
      drm/i915/guc: Remove stale comment for q_fail · 4ca9a582
      Michal Wajdeczko authored
      This member was dropped long time ago.
      
      Fixes: 774439e1 ("drm/i915/guc: re-optimise i915_guc_client layout")
      Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170518113104.54400-1-michal.wajdeczko@intel.comReviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      (cherry picked from commit 4afc67be)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      4ca9a582
    • Thomas Hellstrom's avatar
      drm/vmwgfx: Bump driver minor and date · 1929e661
      Thomas Hellstrom authored
      While the atomic modesetting capability is signaled also elsewhere, also
      reflect it by a driver minor bump.
      Signed-off-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
      1929e661
    • Sinclair Yeh's avatar
      drm/vmwgfx: Remove unused legacy cursor functions · f470a774
      Sinclair Yeh authored
      These function implementations and/or declarations are no longer used
      now that atomic is enabled.
      Signed-off-by: default avatarSinclair Yeh <syeh@vmware.com>
      Reported-by: default avatarDaniel Vetter <daniel@ffwll.ch>
      Reviewed-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
      f470a774
    • Colin Ian King's avatar
      drm/vmwgfx: fix spelling mistake "exeeds" -> "exceeds" · a2e5a3e2
      Colin Ian King authored
      Trivial fix to spelling mistake in DRM_ERROR error message.
      Signed-off-by: default avatarColin Ian King <colin.king@canonical.com>
      Reviewed-by: default avatarSinclair Yeh <syeh@vmware.com>
      a2e5a3e2
    • Sinclair Yeh's avatar
      drm/vmwgfx: Fix large topology crash · a1ac6339
      Sinclair Yeh authored
      The previous attempt at this had an issue with with num_clips > 1
      because it would always end up using the coordinates of the last
      clip while using width and height calculated from the bounding
      box of all the clips.
      
      So if the last clip happens to be not at the top-left corner of
      the bounding box, the CPU blit operation would go out of bounds.
      
      The original intent was to coalesce all the clips into one blit,
      and to do that we need to also track the starting point of the
      content buffer.
      Signed-off-by: default avatarSinclair Yeh <syeh@vmware.com>
      Reviewed-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
      a1ac6339
    • Sinclair Yeh's avatar
      drm/vmwgfx: Make sure to update STDU when FB is updated · 8a309c8a
      Sinclair Yeh authored
      When a new FB is bound, we have to send an update command otherwise
      the new FB may not be shown
      Signed-off-by: default avatarSinclair Yeh <syeh@vmware.com>
      Reviewed-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
      8a309c8a
    • Sinclair Yeh's avatar
      drm/vmwgfx: Make sure backup_handle is always valid · 07678eca
      Sinclair Yeh authored
      When vmw_gb_surface_define_ioctl() is called with an existing buffer,
      we end up returning an uninitialized variable in the backup_handle.
      
      The fix is to first initialize backup_handle to 0 just to be sure, and
      second, when a user-provided buffer is found, we will use the
      req->buffer_handle as the backup_handle.
      
      Cc: <stable@vger.kernel.org>
      Reported-by: default avatarMurray McAllister <murray.mcallister@insomniasec.com>
      Signed-off-by: default avatarSinclair Yeh <syeh@vmware.com>
      Reviewed-by: default avatarDeepak Rawat <drawat@vmware.com>
      07678eca
    • Dan Carpenter's avatar
      drm/vmwgfx: Handle vmalloc() failure in vmw_local_fifo_reserve() · f0c62e98
      Dan Carpenter authored
      If vmalloc() fails then we need to a bit of cleanup before returning.
      
      Cc: <stable@vger.kernel.org>
      Fixes: fb1d9738 ("drm/vmwgfx: Add DRM driver for VMware Virtual GPU")
      Signed-off-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
      Reviewed-by: default avatarSinclair Yeh <syeh@vmware.com>
      f0c62e98
    • Sinclair Yeh's avatar
      drm/vmwgfx: Don't create proxy surface for cursor · bbd5fefe
      Sinclair Yeh authored
      With atomic, the cursor surface is treated like a FB.  Creating
      a proxy surface for cursor doesn't gain us much benefit.
      
      This fixes the issue on atomic enabled 2D VMs where the cursor
      disappears.
      Signed-off-by: default avatarSinclair Yeh <syeh@vmware.com>
      Reviewed-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
      bbd5fefe
    • Vladis Dronov's avatar
      drm/vmwgfx: limit the number of mip levels in vmw_gb_surface_define_ioctl() · ee9c4e68
      Vladis Dronov authored
      The 'req->mip_levels' parameter in vmw_gb_surface_define_ioctl() is
      a user-controlled 'uint32_t' value which is used as a loop count limit.
      This can lead to a kernel lockup and DoS. Add check for 'req->mip_levels'.
      
      References:
      https://bugzilla.redhat.com/show_bug.cgi?id=1437431
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarVladis Dronov <vdronov@redhat.com>
      Reviewed-by: default avatarSinclair Yeh <syeh@vmware.com>
      ee9c4e68
    • Jon Bloomfield's avatar
      drm/i915: Serialize GTT/Aperture accesses on BXT · d86b18a0
      Jon Bloomfield authored
      BXT has a H/W issue with IOMMU which can lead to system hangs when
      Aperture accesses are queued within the GAM behind GTT Accesses.
      
      This patch avoids the condition by wrapping all GTT updates in stop_machine
      and using a flushing read prior to restarting the machine.
      
      The stop_machine guarantees no new Aperture accesses can begin while
      the PTE writes are being emmitted. The flushing read ensures that
      any following Aperture accesses cannot begin until the PTE writes
      have been cleared out of the GAM's fifo.
      
      Only FOLLOWING Aperture accesses need to be separated from in flight
      PTE updates. PTE Writes may follow tightly behind already in flight
      Aperture accesses, so no flushing read is required at the start of
      a PTE update sequence.
      
      This issue was reproduced by running
      	igt/gem_readwrite and
      	igt/gem_render_copy
      simultaneously from different processes, each in a tight loop,
      with INTEL_IOMMU enabled.
      
      This patch was originally published as:
      	drm/i915: Serialize GTT Updates on BXT
      
      [Note: This will cause a performance penalty for some use cases, but
      avoiding hangs trumps performance hits. This may need to be worked
      around in Mesa to recover the lost performance.]
      
      v2: Move bxt/iommu detection into static function
          Remove #ifdef CONFIG_INTEL_IOMMU protection
          Make function names more reflective of purpose
          Move flushing read into static function
      
      v3: Tidy up for checkpatch.pl
      
      Testcase: igt/gem_concurrent_blit
      Signed-off-by: default avatarJon Bloomfield <jon.bloomfield@intel.com>
      Cc: John Harrison <john.C.Harrison@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: stable@vger.kernel.org
      Link: http://patchwork.freedesktop.org/patch/msgid/1495641251-30022-1-git-send-email-jon.bloomfield@intel.comReviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      (cherry picked from commit 0ef34ad6)
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      d86b18a0
    • Julien Grall's avatar
      xen/privcmd: Support correctly 64KB page granularity when mapping memory · 753c09b5
      Julien Grall authored
      Commit 5995a68a "xen/privcmd: Add support for Linux 64KB page granularity" did
      not go far enough to support 64KB in mmap_batch_fn.
      
      The variable 'nr' is the number of 4KB chunk to map. However, when Linux
      is using 64KB page granularity the array of pages (vma->vm_private_data)
      contain one page per 64KB. Fix it by incrementing st->index correctly.
      
      Furthermore, st->va is not correctly incremented as PAGE_SIZE !=
      XEN_PAGE_SIZE.
      
      Fixes: 5995a68a ("xen/privcmd: Add support for Linux 64KB page granularity")
      CC: stable@vger.kernel.org
      Reported-by: default avatarFeng Kan <fkan@apm.com>
      Signed-off-by: default avatarJulien Grall <julien.grall@arm.com>
      Reviewed-by: default avatarBoris Ostrovsky <boris.ostrovsky@oracle.com>
      Signed-off-by: default avatarJuergen Gross <jgross@suse.com>
      753c09b5
  3. 06 Jun, 2017 14 commits