diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h
index e1f91203e7947071b8b0973d7141be2c39476d49..cf18c0808834c7b84ccea6ee9c318d9d754ed587 100644
--- a/arch/arm64/boot/dts/freescale/imx95-clock.h
+++ b/arch/arm64/boot/dts/freescale/imx95-clock.h
@@ -184,4 +184,13 @@
#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8)
#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9)
+#define IMX95_CLK_DISPMIX_ENG0_SEL 0
+#define IMX95_CLK_DISPMIX_ENG1_SEL 1
+#define IMX95_CLK_DISPMIX_END 2
+
+#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0
+#define IMX95_CLK_DISPMIX_LVDS_CH_GATE 1
+#define IMX95_CLK_DISPMIX_PIX_DI_GATE 2
+#define IMX95_CLK_DISPMIX_LVDS_CSR_END 3
+
#endif /* __CLOCK_IMX95_H */
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index d10f62eacfe08d7aa3c7cdd90fbb104b49556c36..cf0a3a1da7cf3f4ffe67f4f910fc32af6d840afa 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1537,6 +1537,497 @@ smmu: iommu@490d0000 {
};
};
+ mipi_dsi: dsi@4acf0000 {
+ compatible = "nxp,imx95-mipi-dsi";
+ reg = <0x0 0x4acf0000 0x0 0x10000>;
+ interrupt-parent = <&displaymix_irqsteer>;
+ interrupts = <48>;
+ clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>,
+ <&scmi_clk IMX95_CLK_MIPIPHYPLLBYPASS>,
+ <&osc_24m>,
+ <&scmi_clk IMX95_CLK_CAMAPB>,
+ <&scmi_clk IMX95_CLK_DISP1PIX>;
+ clock-names = "cfg", "bypass", "ref", "pclk", "pix";
+ assigned-clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>,
+ <&scmi_clk IMX95_CLK_MIPIPHYPLLBYPASS>;
+ assigned-clock-parents = <&osc_24m>,
+ <&scmi_clk IMX95_CLK_VIDEOPLL1>;
+ mux-controls = <&mux 0>;
+ power-domains = <&scmi_devpd IMX95_PD_CAMERA>;
+ nxp,disp-master-csr = <&display_master_csr>;
+ nxp,disp-stream-csr = <&display_stream_csr>;
+ nxp,mipi-combo-phy-csr = <&mipi_tx_phy_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_dsi_to_display_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&display_pixel_link0_to_mipi_dsi>;
+ };
+
+ mipi_dsi_to_display_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&display_pixel_link1_to_mipi_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ display_stream_csr: syscon@4ad00000 {
+ compatible = "nxp,imx95-display-stream-csr", "syscon", "simple-mfd";
+ reg = <0x0 0x4ad00000 0x0 0x10000>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+ };
+
+ display_master_csr: syscon@4ad10000 {
+ compatible = "nxp,imx95-display-master-csr", "syscon";
+ reg = <0x0 0x4ad10000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+ power-domains = <&scmi_devpd IMX95_PD_CAMERA>;
+
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
+ idle-states = <0>;
+ };
+ };
+
+ combo_phy_csr: syscon@4ad20000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x4ad20000 0x0 0x14>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+
+ dphy_rx: dphy-rx {
+ compatible = "fsl,imx95-dphy-rx";
+ clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>;
+ clock-names = "phy_cfg";
+ assigned-clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>;
+ assigned-clock-parents = <&osc_24m>;
+ assigned-clock-rate = <24000000>;
+ #phy-cells = <0>;
+ power-domains = <&scmi_devpd IMX95_PD_CAMERA>;
+ status = "disabled";
+ };
+ };
+
+ mipi_tx_phy_csr: syscon@4ad20100 {
+ compatible = "fsl,imx95-mipi-tx-phy-csr", "syscon";
+ reg = <0x0 0x4ad20100 0x0 0x14>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+ };
+
+ dispmix_csr: syscon@4b010000 {
+ compatible = "nxp,imx95-display-csr", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x4b010000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_DISPAXI>,
+ <&scmi_clk IMX95_CLK_DISPOCRAM>,
+ <&scmi_clk IMX95_CLK_DISPAPB>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <400000000>, <400000000>, <133333333>;
+
+ display_pixel_link: bridge@8 {
+ compatible = "nxp,imx95-dc-pixel-link";
+ reg = <0x8 0x4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ display_pixel_link0_to_pixel_interleaver_disp0: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp0_to_display_pixel_link0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display_pixel_link1_to_pixel_interleaver_disp1: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp1_to_display_pixel_link1>;
+ };
+ };
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ display_pixel_link0_to_mipi_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_dsi_to_display_pixel_link0>;
+ };
+
+ display_pixel_link0_to_ldb_ch0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ldb_ch0_to_display_pixel_link0>;
+ };
+ };
+
+ port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ display_pixel_link1_to_mipi_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_dsi_to_display_pixel_link1>;
+ };
+
+ display_pixel_link1_to_ldb_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ldb_ch1_to_display_pixel_link1>;
+ };
+ };
+ };
+ };
+ };
+
+ displaymix_irqsteer: interrupt-controller@4b0b0000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x0 0x4b0b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, /* reserved */
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, /* reserved */
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <512>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ status = "disabled";
+ };
+
+ lvds_csr: syscon@4b0c0000 {
+ compatible = "nxp,imx95-lvds-csr", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x4b0c0000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+
+ ldb: ldb@4 {
+ compatible = "fsl,imx95-ldb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4 0x4>;
+ clocks = <&lvds_csr IMX95_CLK_DISPMIX_LVDS_CH_GATE>;
+ clock-names = "pixel";
+ status = "disabled";
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&ldb0_phy1>;
+ phy-names = "lvds_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb_ch0_to_display_pixel_link0: endpoint {
+ remote-endpoint = <&display_pixel_link0_to_ldb_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&ldb1_phy1>;
+ phy-names = "lvds_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb_ch1_to_display_pixel_link1: endpoint {
+ remote-endpoint = <&display_pixel_link1_to_ldb_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ ldb0_phy: phy@8 {
+ compatible = "fsl,imx95-lvds0-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x8 0x4>;
+ gpr = <&lvds_csr>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ clock-names = "apb";
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ status = "disabled";
+
+ ldb0_phy1: port@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ldb1_phy: phy@c {
+ compatible = "fsl,imx95-lvds1-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc 0x4>;
+ gpr = <&lvds_csr>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ clock-names = "apb";
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ status = "disabled";
+
+ ldb1_phy1: port@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+
+ pixel_interleaver: bridge@4b0d0000 {
+ compatible = "nxp,imx95-pixel-interleaver";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x4b0d0000 0x0 0x20000>;
+ interrupt-parent = <&displaymix_irqsteer>;
+ interrupts = <62>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ nxp,blk-ctrl = <&dispmix_csr>;
+ status = "disabled";
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ pixel_interleaver_disp0_to_dpu_disp0: endpoint {
+ remote-endpoint = <&dpu_disp0_to_pixel_interleaver_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pixel_interleaver_disp0_to_display_pixel_link0: endpoint {
+ remote-endpoint = <&display_pixel_link0_to_pixel_interleaver_disp0>;
+ };
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ pixel_interleaver_disp1_to_dpu_disp1: endpoint {
+ remote-endpoint = <&dpu_disp1_to_pixel_interleaver_disp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pixel_interleaver_disp1_to_display_pixel_link1: endpoint {
+ remote-endpoint = <&display_pixel_link1_to_pixel_interleaver_disp1>;
+ };
+ };
+ };
+ };
+
+ dpu: display-controller@4b400000 {
+ compatible = "nxp,imx95-dpu";
+ reg = <0x0 0x4b400000 0x0 0x400000>;
+ interrupt-parent = <&displaymix_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <192>, <193>, <194>,
+ <195>, <196>, <197>, <70>,
+ <71>, <72>, <73>, <74>,
+ <75>, <76>, <77>, <78>,
+ <79>, <80>, <81>, <82>,
+ <83>, <84>, <85>, <86>,
+ <87>, <88>, <89>, <90>,
+ <91>, <92>, <198>, <199>,
+ <200>, <201>, <202>, <203>,
+ <204>, <205>, <206>, <207>,
+ <208>, <209>, <210>, <211>,
+ <212>, <451>, <1>, <2>,
+ <3>, <4>, <93>, <94>,
+ <95>, <96>, <97>, <98>,
+ <99>, <100>, <101>, <102>,
+ <103>, <104>, <105>, <106>,
+ <213>, <214>, <215>, <216>,
+ <217>, <218>, <219>, <220>,
+ <221>, <222>, <223>, <224>,
+ <225>, <226>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "domainblend0_shdload",
+ "domainblend0_framecomplete",
+ "domainblend0_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "sig0_cluster_error",
+ "sig0_cluster_match",
+ "sig2_shdload",
+ "sig2_valid",
+ "sig2_error",
+ "sig2_cluster_error",
+ "sig2_cluster_match",
+ "idhash0_shdload",
+ "idhash0_valid",
+ "idhash0_window_error",
+ "domainblend1_shdload",
+ "domainblend1_framecomplete",
+ "domainblend1_seqcomplete",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "sig1_cluster_error",
+ "sig1_cluster_match",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_overflow0_on",
+ "framegen0_overflow0_off",
+ "framegen0_underrun0_on",
+ "framegen0_underrun0_off",
+ "framegen0_threshold0_rise",
+ "framegen0_threshold0_fail",
+ "framegen0_overflow1_on",
+ "framegen0_overflow1_off",
+ "framegen0_underrun1_on",
+ "framegen0_underrun1_off",
+ "framegen0_threshold1_rise",
+ "framegen0_threshold1_fail",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_overflow0_on",
+ "framegen1_overflow0_off",
+ "framegen1_underrun0_on",
+ "framegen1_underrun0_off",
+ "framegen1_threshold0_rise",
+ "framegen1_threshold0_fail",
+ "framegen1_overflow1_on",
+ "framegen1_overflow1_off",
+ "framegen1_underrun1_on",
+ "framegen1_underrun1_off",
+ "framegen1_threshold1_rise",
+ "framegen1_threshold1_fail";
+ clocks = <&scmi_clk IMX95_CLK_DISP1PIX>,
+ <&scmi_clk IMX95_CLK_DISPAPB>,
+ <&scmi_clk IMX95_CLK_DISPAXI>,
+ <&scmi_clk IMX95_CLK_DISPOCRAM>,
+ <&lvds_csr IMX95_CLK_DISPMIX_PIX_DI_GATE>,
+ <&scmi_clk IMX95_CLK_LDBPLL_VCO>;
+ clock-names = "pix", "apb", "axi", "ocram", "ldb", "ldb_vco";
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ nxp,blk-ctrl = <&dispmix_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_disp0_to_pixel_interleaver_disp0: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp0_to_dpu_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_disp1_to_pixel_interleaver_disp1: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp1_to_dpu_disp1>;
+ };
+ };
+ };
+ };
+
+
pcie0: pcie@4c300000 {
compatible = "fsl,imx95-pcie";
reg = <0 0x4c300000 0 0x10000>,