Add USB2 support
- Mar 31, 2023
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Enable USB2 (EHCI and OCHI mode) support for the Radxa ROCK 5 Model B. This adds USB support on the M.2 Key E, both USB2 ports and USB2 mode for the upper USB3 port (the one further away from the PCB). The lower USB3 (closer to the PCB) and the USB-C ports use the RK3588 USB TypeC host controller, which is not yet supported upstream. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> -
Enable USB2 (EHCI and OCHI mode) support for the Rockchip RK3588 EVB1. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>f7b55f1e -
This adds USB2 (EHCI & OHCI) ports including the related PHYs and GRF modules to the rk3588(s) device tree. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>b3158dd8 -
Add support for the USB2 PHY found in the Rockchip RK3588. Co-developed-by:
William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>a8135609 -
Add compatible for the USB2 phy in the Rockchip RK3588 SoC. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>2070fa24 -
The usb2phy is accessible via a syscon registers on RK3588, similar to rk3399. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>f82c94a8 -
Rockchip RK3588 OHCI requires 4 clocks to be enabled. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>67548b45 -
Increase number of allowed clocks to 4, which is the number required on Rockchip RK3588. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>08c06278 -
On RK3588 it's also possible to power down the memory used by the particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds support for this feature. Co-Developed-by:
Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>764e077b -
RK3588 has a couple of hardware blocks called Native Interface Unit (NIU) that gate the clocks to devices behind them. Effectively this means that some clocks require two parent clocks being enabled. Downstream implemented this by using a separate clock driver ("clk-link") for them, which enables the second clock using PM framework. In the upstream kernel we are currently missing support for the second parent. The information about it is in the GATE_LINK() macro as linkname, but that is not used. Thus the second parent clock is not properly enabled. So far this did not really matter, since these clocks are mostly required for the more advanced IP blocks, that are not yet supported upstream. As this is about to change we need a fix. There are three options available: 1. Properly implement support for having two parent clocks in the clock framework. 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not disabled. This wastes some power, but keeps the hack contained within the clock driver. Going from this to the first solution is easy once that has been implemented. 3. Enabling the extra clock in the consumer driver. This leaks some implementation details into DT. This patch implements the second option as an intermediate solution until the first one is available. I used an alias for CLK_IS_CRITICAL, so that it's easy to see which clocks are not really critical once the clock framework supports a better way to implement this. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>460f4976
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