Commit c7bf0a0f authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull Devicetree fixes from Rob Herring:
 "Fix several warnings/errors in validation of binding schemas"

* tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dt-bindings: pinctrl: stm32: Fix missing 'clocks' property in examples
  dt-bindings: iio: ad7124: Fix dtc warnings in example
  dt-bindings: iio: avia-hx711: Fix avdd-supply typo in example
  dt-bindings: pinctrl: aspeed: Fix AST2500 example errors
  dt-bindings: pinctrl: aspeed: Fix 'compatible' schema errors
  dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes
  dt-bindings: Ensure child nodes are of type 'object'
parents d6788eb7 e2297f7c
......@@ -42,6 +42,7 @@ properties:
patternProperties:
"^.*@[0-9a-fA-F]+$":
type: object
properties:
reg:
maxItems: 1
......
......@@ -114,42 +114,47 @@ patternProperties:
examples:
- |
adc@0 {
compatible = "adi,ad7124-4";
reg = <0>;
spi-max-frequency = <5000000>;
interrupts = <25 2>;
interrupt-parent = <&gpio>;
refin1-supply = <&adc_vref>;
clocks = <&ad7124_mclk>;
clock-names = "mclk";
spi {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
adc@0 {
compatible = "adi,ad7124-4";
reg = <0>;
diff-channels = <0 1>;
adi,reference-select = <0>;
adi,buffered-positive;
};
channel@1 {
reg = <1>;
bipolar;
diff-channels = <2 3>;
adi,reference-select = <0>;
adi,buffered-positive;
adi,buffered-negative;
};
channel@2 {
reg = <2>;
diff-channels = <4 5>;
};
channel@3 {
reg = <3>;
diff-channels = <6 7>;
spi-max-frequency = <5000000>;
interrupts = <25 2>;
interrupt-parent = <&gpio>;
refin1-supply = <&adc_vref>;
clocks = <&ad7124_mclk>;
clock-names = "mclk";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
diff-channels = <0 1>;
adi,reference-select = <0>;
adi,buffered-positive;
};
channel@1 {
reg = <1>;
bipolar;
diff-channels = <2 3>;
adi,reference-select = <0>;
adi,buffered-positive;
adi,buffered-negative;
};
channel@2 {
reg = <2>;
diff-channels = <4 5>;
};
channel@3 {
reg = <3>;
diff-channels = <6 7>;
};
};
};
......@@ -61,6 +61,6 @@ examples:
compatible = "avia,hx711";
sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
avdd-suppy = <&avdd>;
avdd-supply = <&avdd>;
clock-frequency = <100000>;
};
......@@ -55,6 +55,7 @@ patternProperties:
"^pinctrl-[0-9]+$": true
"^nand@[a-f0-9]+$":
type: object
properties:
reg:
minimum: 0
......
......@@ -40,6 +40,7 @@ properties:
patternProperties:
"^nand@[a-f0-9]$":
type: object
properties:
reg:
description:
......
......@@ -22,7 +22,9 @@ description: |+
properties:
compatible:
enum: [ aspeed,ast2400-pinctrl, aspeed,g4-pinctrl ]
enum:
- aspeed,ast2400-pinctrl
- aspeed,g4-pinctrl
patternProperties:
'^.*$':
......
......@@ -22,7 +22,9 @@ description: |+
properties:
compatible:
enum: [ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl ]
enum:
- aspeed,ast2500-pinctrl
- aspeed,g5-pinctrl
aspeed,external-nodes:
minItems: 2
maxItems: 2
......@@ -74,9 +76,6 @@ required:
examples:
- |
compatible = "simple-bus";
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -89,7 +88,7 @@ examples:
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
aspeed,external-nodes = <&gfx>, <&lhc>;
pinctrl_i2c3_default: i2c3_default {
function = "I2C3";
......
......@@ -55,6 +55,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
properties:
gpio-controller: true
'#gpio-cells':
......@@ -113,8 +114,10 @@ patternProperties:
- st,bank-name
'-[0-9]*$':
type: object
patternProperties:
'^pins':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl group available on the machine. Each subnode will list the
......@@ -194,6 +197,7 @@ required:
examples:
- |
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>
//Example 1
pinctrl@40020000 {
#address-cells = <1>;
......@@ -207,6 +211,7 @@ examples:
#gpio-cells = <2>;
reg = <0x0 0x400>;
resets = <&reset_ahb1 0>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
};
......@@ -224,6 +229,7 @@ examples:
#gpio-cells = <2>;
reg = <0x1000 0x400>;
resets = <&reset_ahb1 0>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
gpio-ranges = <&pinctrl 0 0 16>;
};
......@@ -233,6 +239,7 @@ examples:
#gpio-cells = <2>;
reg = <0x2000 0x400>;
resets = <&reset_ahb1 0>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
ngpios = <5>;
gpio-ranges = <&pinctrl 0 16 3>,
......
......@@ -10,97 +10,76 @@ maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@sifive.com>
allOf:
- $ref: /schemas/cpus.yaml#
properties:
$nodename:
const: cpus
description: Container of cpu nodes
'#address-cells':
const: 1
description: |
A single unsigned 32-bit integer uniquely identifies each RISC-V
hart in a system. (See the "reg" node under the "cpu" node,
below).
'#size-cells':
const: 0
compatible:
items:
- enum:
- sifive,rocket0
- sifive,e5
- sifive,e51
- sifive,u54-mc
- sifive,u54
- sifive,u5
- const: riscv
description:
Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart.
mmu-type:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- riscv,sv32
- riscv,sv39
- riscv,sv48
description:
Identifies the MMU address translation mode used on this
hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
riscv,isa:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- rv64imac
- rv64imafdc
description:
Identifies the specific RISC-V instruction set architecture
supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
timebase-frequency:
type: integer
minimum: 1
description:
Specifies the clock frequency of the system timer in Hz.
This value is common to all harts on a single system image.
interrupt-controller:
type: object
description: Describes the CPU's local interrupt controller
patternProperties:
'^cpu@[0-9a-f]+$':
properties:
compatible:
type: array
items:
- enum:
- sifive,rocket0
- sifive,e5
- sifive,e51
- sifive,u54-mc
- sifive,u54
- sifive,u5
- const: riscv
description:
Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart.
mmu-type:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- riscv,sv32
- riscv,sv39
- riscv,sv48
description:
Identifies the MMU address translation mode used on this
hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
riscv,isa:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- rv64imac
- rv64imafdc
description:
Identifies the specific RISC-V instruction set architecture
supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
'#interrupt-cells':
const: 1
timebase-frequency:
type: integer
minimum: 1
description:
Specifies the clock frequency of the system timer in Hz.
This value is common to all harts on a single system image.
interrupt-controller:
type: object
description: Describes the CPU's local interrupt controller
properties:
'#interrupt-cells':
const: 1
compatible:
const: riscv,cpu-intc
interrupt-controller: true
compatible:
const: riscv,cpu-intc
required:
- '#interrupt-cells'
- compatible
- interrupt-controller
interrupt-controller: true
required:
- riscv,isa
- timebase-frequency
- '#interrupt-cells'
- compatible
- interrupt-controller
required:
- riscv,isa
- timebase-frequency
- interrupt-controller
examples:
- |
// Example 1: SiFive Freedom U540G Development Kit
......
......@@ -50,6 +50,7 @@ properties:
patternProperties:
"^.*@[0-9a-f]+":
type: object
properties:
reg:
items:
......
......@@ -55,6 +55,7 @@ properties:
patternProperties:
"^.*@[0-9a-f]+":
type: object
properties:
reg:
items:
......
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