From 328329a7bda52a8ed413cd485211463581f7abab Mon Sep 17 00:00:00 2001 From: Anton Vorontsov <avorontsov@ru.mvista.com> Date: Tue, 16 Oct 2007 01:27:47 -0700 Subject: [PATCH] spi_mpc83xx handles other processors with QUICC engine Currently, all QE SPI controllers are almost the same comparing to MPC83xx's, thus let's use that driver for them. Tested to work on MPC85xx in loopback mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> --- drivers/spi/Kconfig | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b91571122daad..a77ede598d341 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC Controller in master SPI mode. config SPI_MPC83xx - tristate "Freescale MPC83xx SPI controller" - depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL + tristate "Freescale MPC83xx/QUICC Engine SPI controller" + depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL select SPI_BITBANG help - This enables using the Freescale MPC83xx SPI controller in master - mode. + This enables using the Freescale MPC83xx and QUICC Engine SPI + controllers in master mode. Note, this driver uniquely supports the SPI controller on the MPC83xx - family of PowerPC processors. The MPC83xx uses a simple set of shift - registers for data (opposed to the CPM based descriptor model). + family of PowerPC processors, plus processors with QUICC Engine + technology. This driver uses a simple set of shift registers for data + (opposed to the CPM based descriptor model). config SPI_OMAP_UWIRE tristate "OMAP1 MicroWire" -- GitLab