diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 9611c91d9b82154e6d5d7f46c75c1b1ab6ffd588..b5d27ec81610333d99868247eebb7ba011e5cca0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -109,6 +109,12 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
#define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
+#ifdef CONFIG_OMAP_GPMC_DEBUG
+#define DEBUG_OMAP_GPMC_HWMOD_FLAGS HWMOD_INIT_NO_RESET
+#else
+#define DEBUG_OMAP_GPMC_HWMOD_FLAGS 0
+#endif
+
#if defined(CONFIG_DEBUG_OMAP2UART1)
#undef DEBUG_OMAP2UART1_FLAGS
#define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 8821b9d6bae432859a6415f5686e10f977e92ae4..6dcfd03ced8faf878746245e8aaf4b45ded3a757 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -762,16 +762,8 @@ struct omap_hwmod omap2xxx_gpmc_hwmod = {
.name = "gpmc",
.class = &omap2xxx_gpmc_hwmod_class,
.main_clk = "gpmc_fck",
- /*
- * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
- * block. It is not being added due to any known bugs with
- * resetting the GPMC IP block, but rather because any timings
- * set by the bootloader are not being correctly programmed by
- * the kernel from the board file or DT data.
- * HWMOD_INIT_NO_RESET should be removed ASAP.
- */
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
- HWMOD_NO_IDLEST),
+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
+ .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.prcm = {
.omap2 = {
.prcm_reg_id = 3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index cabc5695b5043dd3c55db960de5103f4dcdbd2f9..ae0cb673a3d155b326ebd4628989a1f440fc06e6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -668,7 +668,8 @@ struct omap_hwmod am33xx_gpmc_hwmod = {
.name = "gpmc",
.class = &am33xx_gpmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
+ .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.main_clk = "l3s_gclk",
.prcm = {
.omap4 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 4e8e93c398db77ac98c235f38cf57354c5f2ab96..0ca4d3fb7df694f5a095b7822976606a513ce1bb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2169,16 +2169,8 @@ static struct omap_hwmod omap3xxx_gpmc_hwmod = {
.clkdm_name = "core_l3_clkdm",
.mpu_irqs = omap3xxx_gpmc_irqs,
.main_clk = "gpmc_fck",
- /*
- * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
- * block. It is not being added due to any known bugs with
- * resetting the GPMC IP block, but rather because any timings
- * set by the bootloader are not being correctly programmed by
- * the kernel from the board file or DT data.
- * HWMOD_INIT_NO_RESET should be removed ASAP.
- */
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
- HWMOD_NO_IDLEST),
+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
+ .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
};
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f5e68a7820251360dc1aad459e259ee1c6d217ae..43eebf2c59e2f71a375cdbc5d3dbf227f7b99378 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1188,15 +1188,8 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
.name = "gpmc",
.class = &omap44xx_gpmc_hwmod_class,
.clkdm_name = "l3_2_clkdm",
- /*
- * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
- * block. It is not being added due to any known bugs with
- * resetting the GPMC IP block, but rather because any timings
- * set by the bootloader are not being correctly programmed by
- * the kernel from the board file or DT data.
- * HWMOD_INIT_NO_RESET should be removed ASAP.
- */
- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
+ .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 0e64c2fac0b5fad2c92af76a2042a1080108fc04..a0411f32e8b140d54fd0e5f2c4b6a860bd5db699 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -819,8 +819,8 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = {
.name = "gpmc",
.class = &dra7xx_gpmc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
- HWMOD_SWSUP_SIDLE),
+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
+ .flags = HWMOD_SWSUP_SIDLE | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index cab1eb61ac96ef5c2599e85c04f242ad5d54bbf3..c92413769144820f24e1a2cff369ff7910e06f2e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -478,6 +478,8 @@ static struct omap_hwmod dm81xx_gpmc_hwmod = {
.clkdm_name = "alwon_l3s_clkdm",
.class = &dm81xx_gpmc_hwmod_class,
.main_clk = "sysclk6_ck",
+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
+ .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_GPMC_CLKCTRL,
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 868036f70f8f126c0e81e16fe8bd4af63319909a..8406c668ecdc49161795f578e773afeb132058e8 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -49,6 +49,14 @@ config OMAP_GPMC
interfacing to a variety of asynchronous as well as synchronous
memory drives like NOR, NAND, OneNAND, SRAM.
+config OMAP_GPMC_DEBUG
+ bool
+ depends on OMAP_GPMC
+ help
+ Enables verbose debugging mostly to decode the bootloader provided
+ timings. Enable this during development to configure devices
+ connected to the GPMC bus.
+
config MVEBU_DEVBUS
bool "Marvell EBU Device Bus Controller"
default y
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index c94ea0d687467f176e19d44dae06ebe0efaef899..8911e51d410ab3c6e8d14af25fb5c1ff7751b47d 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -403,7 +403,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
p->cycle2cyclediffcsen);
}
-#ifdef DEBUG
+#ifdef CONFIG_OMAP_GPMC_DEBUG
/**
* get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
* @cs: Chip Select Region
@@ -612,7 +612,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max
}
l = gpmc_cs_read_reg(cs, reg);
-#ifdef DEBUG
+#ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info(
"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
@@ -767,7 +767,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
clk_activation, GPMC_CD_FCLK);
-#ifdef DEBUG
+#ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif