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Commit 12082952 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Nicolas Dufresne
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media: cedrus: Fix endless loop in cedrus_h265_skip_bits()


The busy status bit may never de-assert if number of programmed skip
bits is incorrect, resulting in a kernel hang because the bit is polled
endlessly in the code. Fix it by adding timeout for the bit-polling.
This problem is reproducible by setting the data_bit_offset field of
the HEVC slice params to a wrong value by userspace.

Cc: stable@vger.kernel.org
Reported-by: default avatarNicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: default avatarDmitry Osipenko <dmitry.osipenko@collabora.com>
parent 11ebf58e
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...@@ -264,6 +264,7 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, ...@@ -264,6 +264,7 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
{ {
int count = 0; int count = 0;
u32 reg;
while (count < num) { while (count < num) {
int tmp = min(num - count, 32); int tmp = min(num - count, 32);
...@@ -271,8 +272,11 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) ...@@ -271,8 +272,11 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
cedrus_write(dev, VE_DEC_H265_TRIGGER, cedrus_write(dev, VE_DEC_H265_TRIGGER,
VE_DEC_H265_TRIGGER_FLUSH_BITS | VE_DEC_H265_TRIGGER_FLUSH_BITS |
VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp)); VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp));
while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY)
udelay(1); if (read_poll_timeout(cedrus_read, reg,
!(reg & VE_DEC_H265_STATUS_VLD_BUSY),
1, 1000, false, dev, VE_DEC_H265_STATUS))
dev_err_ratelimited(dev->dev, "timed out waiting to skip bits\n");
count += tmp; count += tmp;
} }
......
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