From 2920346e48f01b3e87fc95ecb12e2dca1d662724 Mon Sep 17 00:00:00 2001
From: Darren Etheridge <detheridge@ti.com>
Date: Fri, 28 Jan 2022 15:07:43 -0600
Subject: [PATCH] arm64: dts: ti: k3-j721s2-main: add wave5 video
encoder/decoder node
Add the Chips and Media wave521cl video decoder/encoder node on J721S2.
This functional block also requires an SRAM buffer as a bandwidth saving
temporary store so we need to add a carve out of 126K for this as
specified in the documentation.
Signed-off-by: Darren Etheridge <detheridge@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8915132efcc1b..e4441f4f22073 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -17,6 +17,10 @@
reg = <0x0 0x20000>;
};
+ vpu_sram: vpu-sram@20000 {
+ reg = <0x20000 0x1f800>;
+ };
+
tifs-sram@1f0000 {
reg = <0x1f0000 0x10000>;
};
@@ -348,6 +352,16 @@
status = "disabled";
};
+ vpu: video-codec@4210000 {
+ compatible = "cnm,cm521c-vpu";
+ reg = <0x00 0x4210000 0x00 0x10000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 179 2>;
+ clock-names = "vcodec";
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ sram = <&vpu_sram>;
+ };
+
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
--
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