sun7i-a20.dtsi 39.8 KB
Newer Older
1
2
3
4
5
/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
6
7
8
9
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
10
 *
Maxime Ripard's avatar
Maxime Ripard committed
11
 *  a) This file is free software; you can redistribute it and/or
12
13
14
15
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
Maxime Ripard's avatar
Maxime Ripard committed
16
 *     This file is distributed in the hope that it will be useful,
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
43
44
 */

45
#include "skeleton.dtsi"
46

47
#include <dt-bindings/interrupt-controller/arm-gic.h>
48
#include <dt-bindings/thermal/thermal.h>
49

50
#include <dt-bindings/clock/sun4i-a10-pll2.h>
51
#include <dt-bindings/dma/sun4i-a10.h>
52
#include <dt-bindings/pinctrl/sun4i-a10.h>
53
54
55
56

/ {
	interrupt-parent = <&gic>;

57
	aliases {
58
		ethernet0 = &gmac;
59
60
	};

61
62
63
64
65
	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

66
		framebuffer@0 {
67
68
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
69
			allwinner,pipeline = "de_be0-lcd0-hdmi";
70
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
Chen-Yu Tsai's avatar
Chen-Yu Tsai committed
71
				 <&ahb_gates 44>, <&dram_gates 26>;
72
73
			status = "disabled";
		};
74
75
76
77
78

		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
Chen-Yu Tsai's avatar
Chen-Yu Tsai committed
79
80
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
				 <&dram_gates 26>;
81
82
83
84
85
86
87
			status = "disabled";
		};

		framebuffer@2 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-tve0";
88
89
90
			clocks = <&pll5 1>,
				 <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
				 <&dram_gates 5>, <&dram_gates 26>;
91
92
			status = "disabled";
		};
93
94
	};

95
96
97
98
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

99
		cpu0: cpu@0 {
100
101
102
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
103
104
105
			clocks = <&cpu>;
			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
106
107
108
109
110
111
112
				/* kHz	  uV */
				960000	1400000
				912000	1400000
				864000	1300000
				720000	1200000
				528000	1100000
				312000	1000000
113
				144000	1000000
114
115
116
				>;
			#cooling-cells = <2>;
			cooling-min-level = <0>;
117
			cooling-max-level = <6>;
118
119
120
121
122
123
124
125
126
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

159
160
161
162
	memory {
		reg = <0x40000000 0x80000000>;
	};

Marc Zyngier's avatar
Marc Zyngier committed
163
164
	timer {
		compatible = "arm,armv7-timer";
165
166
167
168
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Marc Zyngier's avatar
Marc Zyngier committed
169
170
	};

171
172
	pmu {
		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
173
174
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
175
176
	};

177
178
179
180
181
	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

182
		osc24M: clk@01c20050 {
183
			#clock-cells = <0>;
184
			compatible = "allwinner,sun4i-a10-osc-clk";
185
			reg = <0x01c20050 0x4>;
186
			clock-frequency = <24000000>;
187
			clock-output-names = "osc24M";
188
189
		};

190
191
192
193
194
195
196
197
198
		osc3M: osc3M_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <8>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc3M";
		};

199
		osc32k: clk@0 {
200
201
202
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
203
			clock-output-names = "osc32k";
204
		};
205

206
		pll1: clk@01c20000 {
207
			#clock-cells = <0>;
208
			compatible = "allwinner,sun4i-a10-pll1-clk";
209
210
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
211
			clock-output-names = "pll1";
212
213
		};

Maxime Ripard's avatar
Maxime Ripard committed
214
215
216
217
218
219
220
221
222
		pll2: clk@01c20008 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll2-clk";
			reg = <0x01c20008 0x8>;
			clocks = <&osc24M>;
			clock-output-names = "pll2-1x", "pll2-2x",
					     "pll2-4x", "pll2-8x";
		};

223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
		pll3: clk@01c20010 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll3-clk";
			reg = <0x01c20010 0x4>;
			clocks = <&osc3M>;
			clock-output-names = "pll3";
		};

		pll3x2: pll3x2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <2>;
			clock-output-names = "pll3-2x";
		};

239
		pll4: clk@01c20018 {
240
			#clock-cells = <0>;
241
			compatible = "allwinner,sun7i-a20-pll4-clk";
Emilio López's avatar
Emilio López committed
242
243
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
244
			clock-output-names = "pll4";
Emilio López's avatar
Emilio López committed
245
246
		};

247
		pll5: clk@01c20020 {
248
			#clock-cells = <1>;
249
			compatible = "allwinner,sun4i-a10-pll5-clk";
250
251
252
253
254
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

255
		pll6: clk@01c20028 {
256
			#clock-cells = <1>;
257
			compatible = "allwinner,sun4i-a10-pll6-clk";
258
259
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
260
261
			clock-output-names = "pll6_sata", "pll6_other", "pll6",
					     "pll6_div_4";
262
263
		};

264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
		pll7: clk@01c20030 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll3-clk";
			reg = <0x01c20030 0x4>;
			clocks = <&osc3M>;
			clock-output-names = "pll7";
		};

		pll7x2: pll7x2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <2>;
			clock-output-names = "pll7-2x";
		};

280
281
282
283
284
285
286
287
		pll8: clk@01c20040 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-pll4-clk";
			reg = <0x01c20040 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll8";
		};

288
289
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
290
			compatible = "allwinner,sun4i-a10-cpu-clk";
291
			reg = <0x01c20054 0x4>;
292
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
293
			clock-output-names = "cpu";
294
295
296
297
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
298
			compatible = "allwinner,sun4i-a10-axi-clk";
299
300
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
301
			clock-output-names = "axi";
302
303
304
305
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
306
			compatible = "allwinner,sun5i-a13-ahb-clk";
307
			reg = <0x01c20054 0x4>;
308
			clocks = <&axi>, <&pll6 3>, <&pll6 1>;
309
			clock-output-names = "ahb";
310
311
312
313
314
315
			/*
			 * Use PLL6 as parent, instead of CPU/AXI
			 * which has rate changes due to cpufreq
			 */
			assigned-clocks = <&ahb>;
			assigned-clock-parents = <&pll6 3>;
316
317
		};

318
		ahb_gates: clk@01c20060 {
319
320
321
322
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
Maxime Ripard's avatar
Maxime Ripard committed
323
324
325
326
327
328
329
330
331
332
333
334
335
			clock-indices = <0>, <1>,
					<2>, <3>, <4>,
					<5>, <6>, <7>, <8>,
					<9>, <10>, <11>, <12>,
					<13>, <14>, <16>,
					<17>, <18>, <20>, <21>,
					<22>, <23>, <25>,
					<28>, <32>, <33>, <34>,
					<35>, <36>, <37>, <40>,
					<41>, <42>, <43>,
					<44>, <45>, <46>,
					<47>, <49>, <50>,
					<52>;
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
				"ahb_nand", "ahb_sdram", "ahb_ace",
				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
				"ahb_spi2", "ahb_spi3", "ahb_sata",
				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
				"ahb_mali";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
353
			compatible = "allwinner,sun4i-a10-apb0-clk";
354
355
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
356
			clock-output-names = "apb0";
357
358
		};

359
		apb0_gates: clk@01c20068 {
360
361
362
363
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
Maxime Ripard's avatar
Maxime Ripard committed
364
365
366
367
			clock-indices = <0>, <1>,
					<2>, <3>, <4>,
					<5>, <6>, <7>,
					<8>, <10>;
368
369
370
371
372
373
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis0", "apb0_iis1",
				"apb0_pio", "apb0_ir0", "apb0_ir1",
				"apb0_iis2", "apb0_keypad";
		};

374
		apb1: clk@01c20058 {
375
			#clock-cells = <0>;
376
			compatible = "allwinner,sun4i-a10-apb1-clk";
377
			reg = <0x01c20058 0x4>;
378
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
379
			clock-output-names = "apb1";
380
381
		};

382
		apb1_gates: clk@01c2006c {
383
384
385
386
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
Maxime Ripard's avatar
Maxime Ripard committed
387
388
389
390
391
392
			clock-indices = <0>, <1>,
					<2>, <3>, <4>,
					<5>, <6>, <7>,
					<15>, <16>, <17>,
					<18>, <19>, <20>,
					<21>, <22>, <23>;
393
394
395
396
397
398
399
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_i2c3", "apb1_can",
				"apb1_scr", "apb1_ps20", "apb1_ps21",
				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3", "apb1_uart4",
				"apb1_uart5", "apb1_uart6", "apb1_uart7";
		};
Emilio López's avatar
Emilio López committed
400
401
402

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
403
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
404
405
406
407
408
409
410
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
411
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
412
413
414
415
416
417
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
418
419
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López's avatar
Emilio López committed
420
421
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
422
423
424
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
Emilio López's avatar
Emilio López committed
425
426
427
		};

		mmc1_clk: clk@01c2008c {
428
429
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López's avatar
Emilio López committed
430
431
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
432
433
434
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
Emilio López's avatar
Emilio López committed
435
436
437
		};

		mmc2_clk: clk@01c20090 {
438
439
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López's avatar
Emilio López committed
440
441
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
442
443
444
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
Emilio López's avatar
Emilio López committed
445
446
447
		};

		mmc3_clk: clk@01c20094 {
448
449
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López's avatar
Emilio López committed
450
451
			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
452
453
454
			clock-output-names = "mmc3",
					     "mmc3_output",
					     "mmc3_sample";
Emilio López's avatar
Emilio López committed
455
456
457
458
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
459
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
460
461
462
463
464
465
466
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
467
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
468
469
470
471
472
473
474
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
475
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
476
477
478
479
480
481
482
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
483
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
484
485
486
487
488
489
490
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
491
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
492
493
494
495
496
497
498
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
499
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
500
501
502
503
504
505
506
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
507
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
508
509
510
511
512
513
514
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
515
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
516
517
518
519
520
			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

521
522
523
524
525
526
527
528
529
530
531
		spdif_clk: clk@01c200c0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200c0 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "spdif";
		};

532
533
534
535
536
537
538
539
		keypad_clk: clk@01c200c4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200c4 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "keypad";
		};

540
541
		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
542
			#reset-cells = <1>;
543
544
545
			compatible = "allwinner,sun4i-a10-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
546
547
			clock-output-names = "usb_ohci0", "usb_ohci1",
					     "usb_phy";
548
549
		};

Emilio López's avatar
Emilio López committed
550
551
		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
552
			compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López's avatar
Emilio López committed
553
554
555
556
			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};
557

Chen-Yu Tsai's avatar
Chen-Yu Tsai committed
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
		dram_gates: clk@01c20100 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-dram-gates-clk";
			reg = <0x01c20100 0x4>;
			clocks = <&pll5 0>;
			clock-indices = <0>,
					<1>, <2>,
					<3>,
					<4>,
					<5>, <6>,
					<15>,
					<24>, <25>,
					<26>, <27>,
					<28>, <29>;
			clock-output-names = "dram_ve",
					     "dram_csi0", "dram_csi1",
					     "dram_ts",
					     "dram_tvd",
					     "dram_tve0", "dram_tve1",
					     "dram_output",
					     "dram_de_fe1", "dram_de_fe0",
					     "dram_de_be0", "dram_de_be1",
					     "dram_de_mp", "dram_ace";
		};

583
584
585
586
587
588
589
590
591
		ve_clk: clk@01c2013c {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-ve-clk";
			reg = <0x01c2013c 0x4>;
			clocks = <&pll4>;
			clock-output-names = "ve";
		};

592
593
594
595
596
597
598
599
		codec_clk: clk@01c20140 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-codec-clk";
			reg = <0x01c20140 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "codec";
		};

600
601
		mbus_clk: clk@01c2015c {
			#clock-cells = <0>;
602
			compatible = "allwinner,sun5i-a13-mbus-clk";
603
604
605
606
			reg = <0x01c2015c 0x4>;
			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
			clock-output-names = "mbus";
		};
607

608
		/*
609
610
611
612
613
614
615
		 * The following two are dummy clocks, placeholders
		 * used in the gmac_tx clock. The gmac driver will
		 * choose one parent depending on the PHY interface
		 * mode, using clk_set_rate auto-reparenting.
		 *
		 * The actual TX clock rate is not controlled by the
		 * gmac_tx clock.
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
		 */
		mii_phy_tx_clk: clk@2 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

		gmac_int_tx_clk: clk@3 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

		gmac_tx_clk: clk@01c20164 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x01c20164 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};

639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
		/*
		 * Dummy clock used by output clocks
		 */
		osc24M_32k: clk@1 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <750>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc24M_32k";
		};

		clk_out_a: clk@01c201f0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f0 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_a";
		};

		clk_out_b: clk@01c201f4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f4 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_b";
		};
666
667
668
669
670
671
672
673
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
		sram-controller@01c00000 {
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_a: sram@00000000 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;

				emac_sram: sram-section@8000 {
					compatible = "allwinner,sun4i-a10-sram-a3-a4";
					reg = <0x8000 0x4000>;
					status = "disabled";
				};
			};

			sram_d: sram@00010000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0000 {
					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

710
711
712
713
714
		nmi_intc: interrupt-controller@01c00030 {
			compatible = "allwinner,sun7i-a20-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01c00030 0x0c>;
715
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
716
717
		};

718
719
720
		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
721
			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
722
723
724
725
			clocks = <&ahb_gates 6>;
			#dma-cells = <2>;
		};

726
727
728
		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
729
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
730
731
			clocks = <&ahb_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
732
733
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
734
			dma-names = "rx", "tx";
735
736
737
738
739
740
741
742
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
743
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
744
745
			clocks = <&ahb_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
746
747
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
748
			dma-names = "rx", "tx";
749
750
751
752
753
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

754
		emac: ethernet@01c0b000 {
755
			compatible = "allwinner,sun4i-a10-emac";
756
			reg = <0x01c0b000 0x1000>;
757
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
758
			clocks = <&ahb_gates 17>;
759
			allwinner,sram = <&emac_sram 1>;
760
761
762
			status = "disabled";
		};

763
		mdio: mdio@01c0b080 {
764
			compatible = "allwinner,sun4i-a10-mdio";
765
766
767
768
769
770
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

771
772
773
		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
774
775
776
777
778
779
780
781
			clocks = <&ahb_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
782
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
783
			status = "disabled";
784
785
			#address-cells = <1>;
			#size-cells = <0>;
786
787
788
789
790
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
791
792
793
794
795
796
797
798
			clocks = <&ahb_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
799
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
800
			status = "disabled";
801
802
			#address-cells = <1>;
			#size-cells = <0>;
803
804
805
806
807
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
808
809
810
811
812
813
814
815
			clocks = <&ahb_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
816
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
817
			status = "disabled";
818
819
			#address-cells = <1>;
			#size-cells = <0>;
820
821
822
823
824
		};

		mmc3: mmc@01c12000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c12000 0x1000>;
825
826
827
828
829
830
831
832
			clocks = <&ahb_gates 11>,
				 <&mmc3_clk 0>,
				 <&mmc3_clk 1>,
				 <&mmc3_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
833
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
834
			status = "disabled";
835
836
			#address-cells = <1>;
			#size-cells = <0>;
837
838
		};

839
840
841
842
843
844
845
846
847
848
849
850
851
		usb_otg: usb@01c13000 {
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
			clocks = <&ahb_gates 0>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

852
853
854
855
856
857
858
		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun7i-a20-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
			reg-names = "phy_ctrl", "pmu1", "pmu2";
			clocks = <&usb_clk 8>;
			clock-names = "usb_phy";
859
860
			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
861
862
863
864
865
866
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
867
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
868
869
870
871
872
873
874
875
876
			clocks = <&ahb_gates 1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
877
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
878
879
880
881
882
883
			clocks = <&usb_clk 6>, <&ahb_gates 2>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

884
885
886
887
888
889
890
891
		crypto: crypto-engine@01c15000 {
			compatible = "allwinner,sun4i-a10-crypto";
			reg = <0x01c15000 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ahb_gates 5>, <&ss_clk>;
			clock-names = "ahb", "mod";
		};

892
893
894
		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
895
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896
897
			clocks = <&ahb_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
898
899
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
900
			dma-names = "rx", "tx";
901
902
903
904
905
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

906
907
908
		ahci: sata@01c18000 {
			compatible = "allwinner,sun4i-a10-ahci";
			reg = <0x01c18000 0x1000>;
909
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
910
911
912
913
			clocks = <&pll6 0>, <&ahb_gates 25>;
			status = "disabled";
		};

914
915
916
		ehci1: usb@01c1c000 {
			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
917
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
918
919
920
921
922
923
924
925
926
			clocks = <&ahb_gates 3>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci1: usb@01c1c400 {
			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
927
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
928
929
930
931
932
933
			clocks = <&usb_clk 7>, <&ahb_gates 4>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

934
935
936
		spi3: spi@01c1f000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c1f000 0x1000>;
937
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
938
939
			clocks = <&ahb_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
940
941
			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
			       <&dma SUN4I_DMA_DEDICATED 30>;
942
			dma-names = "rx", "tx";
943
			status = "disabled";
944
945
946
947
			#address-cells = <1>;
			#size-cells = <0>;
		};

948
949
950
		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
951
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
952
			clocks = <&apb0_gates 5>;
953
954
			gpio-controller;
			interrupt-controller;
955
			#interrupt-cells = <3>;
956
			#gpio-cells = <3>;
957

958
959
960
			pwm0_pins_a: pwm0@0 {
				allwinner,pins = "PB2";
				allwinner,function = "pwm";
961
962
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
963
964
965
966
967
			};

			pwm1_pins_a: pwm1@0 {
				allwinner,pins = "PI3";
				allwinner,function = "pwm";
968
969
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
970
971
			};

972
973
974
			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
975
976
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
977
978
			};

979
980
981
			uart2_pins_a: uart2@0 {
				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
				allwinner,function = "uart2";
982
983
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
984
985
			};

986
987
988
			uart3_pins_a: uart3@0 {
				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
				allwinner,function = "uart3";
989
990
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
991
992
			};

993
994
995
			uart3_pins_b: uart3@1 {
				allwinner,pins = "PH0", "PH1";
				allwinner,function = "uart3";
996
997
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
998
999
			};

1000
1001
1002
			uart4_pins_a: uart4@0 {
				allwinner,pins = "PG10", "PG11";
				allwinner,function = "uart4";
1003
1004
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1005
1006
			};

1007
1008
1009
1010
1011
1012
1013
			uart4_pins_b: uart4@1 {
				allwinner,pins = "PH4", "PH5";
				allwinner,function = "uart4";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

1014
1015
1016
			uart5_pins_a: uart5@0 {
				allwinner,pins = "PI10", "PI11";
				allwinner,function = "uart5";
1017
1018
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1019
1020
			};

1021
1022
1023
			uart6_pins_a: uart6@0 {
				allwinner,pins = "PI12", "PI13";
				allwinner,function = "uart6";
1024
1025
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1026
1027
1028
1029
1030
			};

			uart7_pins_a: uart7@0 {
				allwinner,pins = "PI20", "PI21";
				allwinner,function = "uart7";
1031
1032
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1033
			};
1034

1035
1036
1037
			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
1038
1039
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1040
1041
1042
1043
1044
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
1045
1046
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1047
1048
1049
1050
1051
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
1052
1053
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1054
1055
			};

1056
1057
1058
			i2c3_pins_a: i2c3@0 {
				allwinner,pins = "PI0", "PI1";
				allwinner,function = "i2c3";
1059
1060
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1061
1062
			};

1063
1064
1065
1066
1067
1068
1069
			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
1070
1071
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1072
			};
1073
1074
1075
1076

			clk_out_a_pins_a: clk_out_a@0 {
				allwinner,pins = "PI12";
				allwinner,function = "clk_out_a";
1077
1078
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1079
1080
1081
1082
1083
			};

			clk_out_b_pins_a: clk_out_b@0 {
				allwinner,pins = "PI13";
				allwinner,function = "clk_out_b";
1084
1085
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1086
			};
1087
1088
1089
1090
1091
1092
1093
1094

			gmac_pins_mii_a: gmac_mii@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "gmac";
1095
1096
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
			};

			gmac_pins_rgmii_a: gmac_rgmii@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA10",
						"PA11", "PA12", "PA13",
						"PA15", "PA16";
				allwinner,function = "gmac";
				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
1110
1111
				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1112
			};
1113

1114
			spi0_pins_a: spi0@0 {
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
				allwinner,pins = "PI11", "PI12", "PI13";
				allwinner,function = "spi0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi0_cs0_pins_a: spi0_cs0@0 {
				allwinner,pins = "PI10";
				allwinner,function = "spi0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi0_cs1_pins_a: spi0_cs1@0 {
				allwinner,pins = "PI14";
1130
				allwinner,function = "spi0";
1131
1132
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1133
1134
			};

1135
			spi1_pins_a: spi1@0 {
1136
1137
1138
1139
1140
1141
1142
1143
				allwinner,pins = "PI17", "PI18", "PI19";
				allwinner,function = "spi1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi1_cs0_pins_a: spi1_cs0@0 {
				allwinner,pins = "PI16";
1144
				allwinner,function = "spi1";
1145
1146
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1147
1148
1149
			};

			spi2_pins_a: spi2@0 {
1150
				allwinner,pins = "PC20", "PC21", "PC22";
1151
				allwinner,function = "spi2";
1152
1153
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1154
1155
1156
			};

			spi2_pins_b: spi2@1 {
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
				allwinner,pins = "PB15", "PB16", "PB17";
				allwinner,function = "spi2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi2_cs0_pins_a: spi2_cs0@0 {
				allwinner,pins = "PC19";
				allwinner,function = "spi2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi2_cs0_pins_b: spi2_cs0@1 {
				allwinner,pins = "PB14";
1172
				allwinner,function = "spi2";
1173
1174
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1175
			};
1176
1177

			mmc0_pins_a: mmc0@0 {
1178
1179
				allwinner,pins = "PF0", "PF1", "PF2",
						 "PF3", "PF4", "PF5";
1180
				allwinner,function = "mmc0";
1181
1182
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1183
1184
1185
1186
1187
			};

			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
				allwinner,pins = "PH1";
				allwinner,function = "gpio_in";
1188
1189
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1190
1191
			};

1192
			mmc2_pins_a: mmc2@0 {
1193
1194
				allwinner,pins = "PC6", "PC7", "PC8",
						 "PC9", "PC10", "PC11";
1195
				allwinner,function = "mmc2";
1196
1197
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1198
1199
			};

1200
			mmc3_pins_a: mmc3@0 {
1201
1202
				allwinner,pins = "PI4", "PI5", "PI6",
						 "PI7", "PI8", "PI9";
1203
				allwinner,function = "mmc3";
1204
1205
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1206
			};
1207

1208
1209
			ir0_rx_pins_a: ir0@0 {
				    allwinner,pins = "PB4";
1210
				    allwinner,function = "ir0";
1211
1212
				    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1213
1214
			};

1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
			ir0_tx_pins_a: ir0@1 {
				    allwinner,pins = "PB3";
				    allwinner,function = "ir0";
				    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			ir1_rx_pins_a: ir1@0 {
				    allwinner,pins = "PB23";
				    allwinner,function = "ir1";
				    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			ir1_tx_pins_a: ir1@1 {
				    allwinner,pins = "PB22";
1231
				    allwinner,function = "ir1";
1232
1233
				    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1234
			};
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247

			ps20_pins_a: ps20@0 {
				allwinner,pins = "PI20", "PI21";
				allwinner,function = "ps2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			ps21_pins_a: ps21@0 {
				allwinner,pins = "PH12", "PH13";
				allwinner,function = "ps2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1248
			};
1249
1250
1251
1252
1253
1254
1255

			spdif_tx_pins_a: spdif@0 {
				allwinner,pins = "PB13";
				allwinner,function = "spdif";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};
1256
1257
		};

1258
		timer@01c20c00 {
1259
			compatible = "allwinner,sun4i-a10-timer";
1260
			reg = <0x01c20c00 0x90>;
1261
1262
1263
1264
1265
1266
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1267
1268
1269
1270
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
1271
			compatible = "allwinner,sun4i-a10-wdt";
1272
1273
1274
			reg = <0x01c20c90 0x10>;
		};

1275
1276
1277
		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun7i-a20-rtc";
			reg = <0x01c20d00 0x20>;
1278
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1279
1280
		};

1281
1282
1283
1284
1285
1286
1287
1288
		pwm: pwm@01c20e00 {
			compatible = "allwinner,sun7i-a20-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
		spdif: spdif@01c21000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-spdif";
			reg = <0x01c21000 0x400>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 1>, <&spdif_clk>;
			clock-names = "apb", "spdif";
			dmas = <&dma SUN4I_DMA_NORMAL 2>,
			       <&dma SUN4I_DMA_NORMAL 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1302
		ir0: ir@01c21800 {
1303
			compatible = "allwinner,sun4i-a10-ir";
1304
1305
			clocks = <&apb0_gates 6>, <&ir0_clk>;
			clock-names = "apb", "ir";
1306
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1307
1308
1309
1310
1311
			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

		ir1: ir@01c21c00 {
1312
			compatible = "allwinner,sun4i-a10-ir";
1313
1314
			clocks = <&apb0_gates 7>, <&ir1_clk>;
			clock-names = "apb", "ir";
1315
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1316
1317
1318
1319
			reg = <0x01c21c00 0x40>;
			status = "disabled";
		};

1320
1321
1322
		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
1323
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1324
1325
1326
			status = "disabled";
		};

1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
		codec: codec@01c22c00 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun7i-a20-codec";
			reg = <0x01c22c00 0x40>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 0>, <&codec_clk>;
			clock-names = "apb", "codec";
			dmas = <&dma SUN4I_DMA_NORMAL 19>,
			       <&dma SUN4I_DMA_NORMAL 19>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1340
1341
1342
1343
1344
		sid: eeprom@01c23800 {
			compatible = "allwinner,sun7i-a20-sid";
			reg = <0x01c23800 0x200>;
		};

1345
		rtp: rtp@01c25000 {
1346
			compatible = "allwinner,sun5i-a13-ts";
1347
			reg = <0x01c25000 0x100>;
1348
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1349
			#thermal-sensor-cells = <0>;
1350
1351
		};

1352
1353
1354
		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
1355
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1356
1357
			reg-shift = <2>;
			reg-io-width = <4>;
1358
			clocks = <&apb1_gates 16>;
1359
1360
1361
1362
1363
1364
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
1365
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1366
1367
			reg-shift = <2>;
			reg-io-width = <4>;
1368
			clocks = <&apb1_gates 17>;
1369
1370
1371
1372
1373
1374
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
1375
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1376
1377
			reg-shift = <2>;
			reg-io-width = <4>;
1378
			clocks = <&apb1_gates 18>;
1379
1380
1381
1382
1383
1384
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
1385
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1386
1387
			reg-shift = <2>;
			reg-io-width = <4>;
1388
			clocks = <&apb1_gates 19>;
1389
1390
1391
1392
1393
1394
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
1395
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1396
1397
			reg-shift = <2>;
			reg-io-width = <4>;
1398
			clocks = <&apb1_gates 20>;
1399
1400
1401
1402
1403
1404
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
1405
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1406
1407
			reg-shift = <2>;
			reg-io-width = <4>;
1408
			clocks = <&apb1_gates 21>;
1409
1410
1411
1412
1413
1414
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
1415
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1416
1417
			reg-shift = <2>;
			reg-io-width = <4>;
1418
			clocks = <&apb1_gates 22>;
1419
1420
1421
1422
1423
1424
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;