qcom,pcie.txt 8.2 KB
Newer Older
1 2 3 4 5 6 7 8 9
* Qualcomm PCI express root complex

- compatible:
	Usage: required
	Value type: <stringlist>
	Definition: Value should contain
			- "qcom,pcie-ipq8064" for ipq8064
			- "qcom,pcie-apq8064" for apq8064
			- "qcom,pcie-apq8084" for apq8084
10
			- "qcom,pcie-msm8996" for msm8996 or apq8096
11
			- "qcom,pcie-ipq4019" for ipq4019
12
			- "qcom,pcie-ipq8074" for ipq8074
13 14 15 16 17 18 19 20 21 22 23

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: Register ranges as listed in the reg-names property

- reg-names:
	Usage: required
	Value type: <stringlist>
	Definition: Must include the following entries
			- "parf"   Qualcomm specific registers
24
			- "dbi"	   DesignWare PCIe registers
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
			- "elbi"   External local bus interface registers
			- "config" PCIe configuration space

- device_type:
	Usage: required
	Value type: <string>
	Definition: Should be "pci". As specified in designware-pcie.txt

- #address-cells:
	Usage: required
	Value type: <u32>
	Definition: Should be 3. As specified in designware-pcie.txt

- #size-cells:
	Usage: required
	Value type: <u32>
	Definition: Should be 2. As specified in designware-pcie.txt

- ranges:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: As specified in designware-pcie.txt

- interrupts:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: MSI interrupt

- interrupt-names:
	Usage: required
	Value type: <stringlist>
	Definition: Should contain "msi"

- #interrupt-cells:
	Usage: required
	Value type: <u32>
	Definition: Should be 1. As specified in designware-pcie.txt

- interrupt-map-mask:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: As specified in designware-pcie.txt

- interrupt-map:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: As specified in designware-pcie.txt

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: List of phandle and clock specifier pairs as listed
		    in clock-names property

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "iface"	Configuration AHB clock

- clock-names:
	Usage: required for ipq/apq8064
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "core"	Clocks the pcie hw block
			- "phy"		Clocks the pcie PHY block
- clock-names:
92
	Usage: required for apq8084/ipq4019
93 94 95 96 97
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "aux"		Auxiliary (AUX) clock
			- "bus_master"	Master AXI clock
			- "bus_slave"	Slave AXI clock
98 99 100 101 102 103 104 105 106 107 108

- clock-names:
	Usage: required for msm8996/apq8096
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "pipe"	Pipe Clock driving internal logic
			- "aux"		Auxiliary (AUX) clock
			- "cfg"		Configuration clock
			- "bus_master"	Master AXI clock
			- "bus_slave"	Slave AXI clock

109 110 111 112 113 114 115 116 117 118
- clock-names:
	Usage: required for ipq8074
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "iface"	PCIe to SysNOC BIU clock
			- "axi_m"	AXI Master clock
			- "axi_s"	AXI Slave clock
			- "ahb"		AHB clock
			- "aux"		Auxiliary clock

119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
- resets:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: List of phandle and reset specifier pairs as listed
		    in reset-names property

- reset-names:
	Usage: required for ipq/apq8064
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "axi"  AXI reset
			- "ahb"  AHB reset
			- "por"  POR reset
			- "pci"  PCI reset
			- "phy"  PHY reset

- reset-names:
	Usage: required for apq8084
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "core" Core reset

141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157
- reset-names:
	Usage: required for ipq/apq8064
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "axi_m"		AXI master reset
			- "axi_s"		AXI slave reset
			- "pipe"		PIPE reset
			- "axi_m_vmid"		VMID reset
			- "axi_s_xpu"		XPU reset
			- "parf"		PARF reset
			- "phy"			PHY reset
			- "axi_m_sticky"	AXI sticky reset
			- "pipe_sticky"		PIPE sticky reset
			- "pwr"			PWR reset
			- "ahb"			AHB reset
			- "phy_ahb"		PHY AHB reset

158 159 160 161 162 163 164 165 166 167 168 169
- reset-names:
	Usage: required for ipq8074
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "pipe"		PIPE reset
			- "sleep"		Sleep reset
			- "sticky"		Core Sticky reset
			- "axi_m"		AXI Master reset
			- "axi_s"		AXI Slave reset
			- "ahb"			AHB Reset
			- "axi_m_sticky"	AXI Master Sticky reset

170
- power-domains:
171
	Usage: required for apq8084 and msm8996/apq8096
172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
	Value type: <prop-encoded-array>
	Definition: A phandle and power domain specifier pair to the
		    power domain which is responsible for collapsing
		    and restoring power to the peripheral

- vdda-supply:
	Usage: required
	Value type: <phandle>
	Definition: A phandle to the core analog power supply

- vdda_phy-supply:
	Usage: required for ipq/apq8064
	Value type: <phandle>
	Definition: A phandle to the analog power supply for PHY

- vdda_refclk-supply:
	Usage: required for ipq/apq8064
	Value type: <phandle>
	Definition: A phandle to the analog power supply for IC which generates
		    reference clock
192 193 194 195
- vddpe-3v3-supply:
	Usage: optional
	Value type: <phandle>
	Definition: A phandle to the PCIe endpoint power supply
196 197 198 199 200 201 202 203 204 205 206 207 208 209

- phys:
	Usage: required for apq8084
	Value type: <phandle>
	Definition: List of phandle(s) as listed in phy-names property

- phy-names:
	Usage: required for apq8084
	Value type: <stringlist>
	Definition: Should contain "pciephy"

- <name>-gpios:
	Usage: optional
	Value type: <prop-encoded-array>
210
	Definition: List of phandle and GPIO specifier pairs. Should contain
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290
			- "perst-gpios"	PCIe endpoint reset signal line
			- "wake-gpios"	PCIe endpoint wake signal line

* Example for ipq/apq8064
	pcie@1b500000 {
		compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
		reg = <0x1b500000 0x1000
		       0x1b502000 0x80
		       0x1b600000 0x100
		       0x0ff00000 0x100000>;
		reg-names = "dbi", "elbi", "parf", "config";
		device_type = "pci";
		linux,pci-domain = <0>;
		bus-range = <0x00 0xff>;
		num-lanes = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
		clocks = <&gcc PCIE_A_CLK>,
			 <&gcc PCIE_H_CLK>,
			 <&gcc PCIE_PHY_CLK>;
		clock-names = "core", "iface", "phy";
		resets = <&gcc PCIE_ACLK_RESET>,
			 <&gcc PCIE_HCLK_RESET>,
			 <&gcc PCIE_POR_RESET>,
			 <&gcc PCIE_PCI_RESET>,
			 <&gcc PCIE_PHY_RESET>;
		reset-names = "axi", "ahb", "por", "pci", "phy";
		pinctrl-0 = <&pcie_pins_default>;
		pinctrl-names = "default";
	};

* Example for apq8084
	pcie0@fc520000 {
		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
		reg = <0xfc520000 0x2000>,
		      <0xff000000 0x1000>,
		      <0xff001000 0x1000>,
		      <0xff002000 0x2000>;
		reg-names = "parf", "dbi", "elbi", "config";
		device_type = "pci";
		linux,pci-domain = <0>;
		bus-range = <0x00 0xff>;
		num-lanes = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
			  0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
		interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
				<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
				<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
				<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
		clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
			 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
			 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
			 <&gcc GCC_PCIE_0_AUX_CLK>;
		clock-names = "iface", "master_bus", "slave_bus", "aux";
		resets = <&gcc GCC_PCIE_0_BCR>;
		reset-names = "core";
		power-domains = <&gcc PCIE0_GDSC>;
		vdda-supply = <&pma8084_l3>;
		phys = <&pciephy0>;
		phy-names = "pciephy";
		perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
		pinctrl-0 = <&pcie0_pins_default>;
		pinctrl-names = "default";
	};